UCC5350-Q1

現行

適用於 IGBT/SiC 且具米勒箝位或分離輸出的車用 ±5-A 單通道絕緣式閘極驅動器

產品詳細資料

Number of channels 1 Isolation rating Basic, Reinforced Withstand isolation voltage (VISO) (Vrms) 3000, 5000 Working isolation voltage (VIOWM) (Vrms) 990, 2121 Transient isolation voltage (VIOTM) (VPK) 4242, 7000 Power switch IGBT, MOSFET, SiCFET Peak output current (A) 10 Features Active miller clamp, Split output Output VCC/VDD (max) (V) 33 Output VCC/VDD (min) (V) 9.5 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 15 TI functional safety category Functional Safety-Capable Propagation delay time (µs) 0.065 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Automotive, Catalog Bootstrap supply voltage (max) (V) 990 Rise time (ns) 10 Fall time (ns) 10 Undervoltage lockout (typ) (V) 8, 12
Number of channels 1 Isolation rating Basic, Reinforced Withstand isolation voltage (VISO) (Vrms) 3000, 5000 Working isolation voltage (VIOWM) (Vrms) 990, 2121 Transient isolation voltage (VIOTM) (VPK) 4242, 7000 Power switch IGBT, MOSFET, SiCFET Peak output current (A) 10 Features Active miller clamp, Split output Output VCC/VDD (max) (V) 33 Output VCC/VDD (min) (V) 9.5 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 15 TI functional safety category Functional Safety-Capable Propagation delay time (µs) 0.065 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Automotive, Catalog Bootstrap supply voltage (max) (V) 990 Rise time (ns) 10 Fall time (ns) 10 Undervoltage lockout (typ) (V) 8, 12
SOIC (D) 8 29.4 mm² 4.9 x 6 SOIC (DWV) 8 67.275 mm² 5.85 x 11.5
  • 5kVRMS and 3kVRMS single-channel isolated gate driver
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1
    • HBM ESD classification level H2
    • CDM ESD classification level C6
  • Feature options
    • Split outputs, 8V UVLO (UCC5350SB-Q1)
    • Miller clamp, 12V UVLO (UCC5350MC-Q1)
  • ±5A minimum peak current drive strength
  • 3V to 15V input supply voltage
  • Up to 33V driver supply voltage
    • 8V and 12V UVLO options
  • 100V/ns minimum CMTI
  • Negative 5V handling capability on input pins
  • 100ns (maximum) propagation delay and <25ns part-to-part skew
  • 8-pin DWV (8.5mm creepage) and D (4mm creepage) packages
  • Isolation barrier life > 40 Years
  • Safety-related certifications:
    • 5000VRMS DWV and 3000VRMS D isolation rating for 1 minute per UL 1577
  • CMOS inputs
  • Operating junction temperature: –40°C to +150°C
  • 5kVRMS and 3kVRMS single-channel isolated gate driver
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1
    • HBM ESD classification level H2
    • CDM ESD classification level C6
  • Feature options
    • Split outputs, 8V UVLO (UCC5350SB-Q1)
    • Miller clamp, 12V UVLO (UCC5350MC-Q1)
  • ±5A minimum peak current drive strength
  • 3V to 15V input supply voltage
  • Up to 33V driver supply voltage
    • 8V and 12V UVLO options
  • 100V/ns minimum CMTI
  • Negative 5V handling capability on input pins
  • 100ns (maximum) propagation delay and <25ns part-to-part skew
  • 8-pin DWV (8.5mm creepage) and D (4mm creepage) packages
  • Isolation barrier life > 40 Years
  • Safety-related certifications:
    • 5000VRMS DWV and 3000VRMS D isolation rating for 1 minute per UL 1577
  • CMOS inputs
  • Operating junction temperature: –40°C to +150°C

The UCC5350-Q1 is a single-channel, isolated gate driver with 5A source and 5A sink minimum peak current designed to drive MOSFETs, IGBTs, and SiC MOSFETs. The UCC5350-Q1 has the option for Miller clamp or Split Outputs. The CLAMP pin is used to connect the transistor gate to an internal FET besides the output to prevent false turn-on caused by Miller current. The split outputs option allows separate control of the rise and fall times of the gate voltage with OUTH and OUTL pins.

The UCC5350-Q1 is a single-channel, isolated gate driver with 5A source and 5A sink minimum peak current designed to drive MOSFETs, IGBTs, and SiC MOSFETs. The UCC5350-Q1 has the option for Miller clamp or Split Outputs. The CLAMP pin is used to connect the transistor gate to an internal FET besides the output to prevent false turn-on caused by Miller current. The split outputs option allows separate control of the rise and fall times of the gate voltage with OUTH and OUTL pins.

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* Data sheet UCC5350-Q1 Single-Channel Isolated Gate Driver for SiC/IGBT and Automotive Applications datasheet (Rev. E) PDF | HTML 2024年 2月 5日
Functional safety information UCC5390-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA PDF | HTML 2022年 3月 16日
Technical article Increasing power density with an integrated GaN solution PDF | HTML 2022年 3月 14日
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 2021年 12月 16日

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隔離式閘極驅動器
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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