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Product details

Parameters

Vin (Min) (V) 2.95 Vin (Max) (V) 6 Vout (Min) (V) 0.8 Vout (Max) (V) 4.5 Iout (Max) (A) 3 Regulated outputs (#) 1 Switching frequency (Min) (kHz) 200 Switching frequency (Max) (kHz) 2000 Features Enable, Frequency Synchronization, Power Good, Pre-Bias Start-Up, Synchronous Rectification, UVLO Adjustable, Soft Start Adjustable Control mode Current Mode Duty cycle (Max) (%) 98 Type Converter Operating temperature range (C) -40 to 150 Rating Catalog open-in-new Find other Buck converters (integrated switch)

Package | Pins | Size

WQFN (RTE) 16 9 mm² 3 x 3 open-in-new Find other Buck converters (integrated switch)

Features

  • Two, 30-mΩ (typical) MOSFETs for High-Efficiency at 3-A loads
  • Switching Frequency: 200 kHz to 2 MHz
  • Voltage Reference Over Temperature: 0.8 V ± 1%
  • Synchronizes to External Clock
  • Adjustable Soft Start/Sequencing
  • UV and OV Power-Good Output
  • Low Operating and Shutdown Quiescent Current
  • Safe Start-Up into Prebiased Output
  • Cycle-by-Cycle Current Limit, Thermal and Frequency Foldback Protection
  • Operating Junction Temperature Range: –40°C to 150°C
  • Thermally Enhanced 3 mm × 3 mm 16-pin WQFN Package
  • Create a Custom Design Using the TPS54318 With the WEBENCH® Power Designer

All trademarks are the property of their respective owners.

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Description

TheTPS54318 device is a full-featured, 6-V, 3-A, synchronous, step-down current-mode converter with two integrated MOSFETs.

The TPS54318 device enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2-MHz switching frequency, and minimizing the device footprint with a small, 3 mm x 3 mm, thermally enhanced, QFN package.

The TPS54318 device provides accurate regulation for a variety of loads with an accurate ±1% voltage reference (VREF) over temperature.

Efficiency is maximized through the integrated 30-mΩ MOSFETs and a 350-µA typical supply current. Using the EN pin, shutdown supply current is reduced to 2 µA by entering a shutdown mode.

Undervoltage lockout is internally set at 2.6 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the soft-start pin. An open-drain power-good signal indicates the output is within 93% to 107% of its nominal voltage. Frequency foldback and thermal shutdown protects the device during an overcurrent condition.

For more SWIFT™ documentation, see the TI website at www.ti.com/swift.

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Technical documentation

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Type Title Date
* Datasheet TPS54318 2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Converter datasheet (Rev. C) Apr. 06, 2018
Selection guides Buck Converter Quick Reference Guide (Rev. A) Mar. 31, 2020
Application notes Calculating Efficiency (Rev. A) Mar. 06, 2020
Technical articles Minimize the impact of the MLCC shortage on your power application Mar. 29, 2019
Selection guides SWIFT DC/DC Converters Selector Guide (Rev. G) Feb. 06, 2019
Application notes Semiconductor and IC Package Thermal Metrics (Rev. C) Apr. 19, 2016
Selection guides Analog for Xilinx (R) FPGAs Selection Guide - 2015 (Rev. B) Jan. 07, 2015
Selection guides Power Management for Xilinx FPGAs Feb. 04, 2014
Selection guides TI's Compact Power Solution for Avnet's Xilinx Kintex-7 FPGA Board Mar. 14, 2012
Selection guides Power Management for Altera FPGAs (Rev. E) Feb. 22, 2012
Application notes Understanding Thermal Dissipation and Design of a Heatsink May 04, 2011
Selection guides Power Management for Altera Cyclone FPGAs (Rev. A) Mar. 15, 2011
Application notes Designing Type III Compensation for Current Mode Step-Down Converters (Rev. A) Sep. 15, 2010
User guides TPS54318EVM-512 3-A, SWIFT Regulator Evaluation Module Sep. 23, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$25.00
Description
The TPS54318EVM-512 evaluation module is designed to demonstrate the small printed-circuit-board areas that may be achieved when designing with the TPS54318 regulator. The TPS54318 dc/dc converter is designed to provide up to a 3 A output from an input voltage source of 2.95 V to 6 V. Rated input (...)

Design tools & simulation

SIMULATION MODELS Download
SLVM640A.ZIP (54 KB) - PSpice Model
SIMULATION MODELS Download
SLVM651.TSC (172 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLVM652.ZIP (63 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SLVM897A.ZIP (36 KB) - PSpice Model
CALCULATION TOOLS Download
TPS54620 & TPS54XXX Current-Mode Step-Down Converter Design Calculator
TPS54620DESIGN-CALC — The Design Calculator Plus Application Note (SLVA352A) Calculator Tool calculates the critical external component values for the TPS54620/TPS54622/TPS54521/TPS54320/TPS54618/TPS54418/TPS54318/TPS54218/TPS54319. The calculator includes power stage design, feature design and Type II and Type III (...)
SCHEMATICS Download
SLTR012.PDF (50 KB)
SCHEMATICS Download
SLTR028.PDF (38 KB)

Reference designs

REFERENCE DESIGNS Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (RTE) 16 View options

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