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Product details

Parameters

Function Fanout Additive RMS jitter (Typ) (fs) 51 Output frequency (Max) (MHz) 3100 Number of outputs 5 Output supply voltage (V) 3.3, 2.5 Core supply voltage (V) 3.3 Output skew (ps) 50 Features Pin programmable Operating temperature range (C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL open-in-new Find other Clock buffers

Package | Pins | Size

WQFN (RTV) 32 25 mm² 5 x 5 open-in-new Find other Clock buffers

Features

  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 2 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable)
    • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: –65 / –76 dBc (LVPECL/LVDS) at 156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 32-lead WQFN (5 mm × 5 mm)

All trademarks are the property of their respective owners.

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Description

The LMK00304 is a 3-GHz 4-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 differential outputs and one LVCMOS output. The differential output banks can be mutually configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00304 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00304 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet LMK00304 3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator datasheet (Rev. G) Aug. 13, 2018
Technical articles Measuring additive jitter in fanout buffers Feb. 07, 2014
User guides LMK00304 Evaluation Module User Guide Mar. 06, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
249
Description

Description:

The LMK00304 Evaluation Board allows functional and performance verification of the LMK00304 high-performance 4-output differential clock buffer device.

Features:

  • Low-noise clock fan-out with two banks of two differential outputs each and one LVCMOS output
  • Selectable differential output (...)

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
Clock Design Tool - Loop Filter & Device Configuration + Simulation
CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

Design tools & simulation

SIMULATION MODELS Download
SNAM051A.ZIP (102 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

REFERENCE DESIGNS Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132 — This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (RTV) 32 View options

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