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LMK00304

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3.1-GHz differential clock buffer/level translator with 4 configurable outputs

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Data sheet

LMK00304

ACTIVE
Data sheet Order now

Product details

Number of outputs 5 Additive RMS jitter (typ) (fs) 51 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
Number of outputs 5 Additive RMS jitter (typ) (fs) 51 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
WQFN (RTV) 32 25 mm² 5 x 5
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 2 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable)
    • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: –65 / –76 dBc (LVPECL/LVDS) at 156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 32-lead WQFN (5 mm × 5 mm)
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 2 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable)
    • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: –65 / –76 dBc (LVPECL/LVDS) at 156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 32-lead WQFN (5 mm × 5 mm)

The LMK00304 is a 3-GHz 4-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 differential outputs and one LVCMOS output. The differential output banks can be mutually configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00304 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00304 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00304 is a 3-GHz 4-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 differential outputs and one LVCMOS output. The differential output banks can be mutually configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00304 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00304 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
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* Data sheet LMK00304 3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator datasheet (Rev. G) PDF | HTML 13 Aug 2018
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023
Application note Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter PDF | HTML 30 Sep 2020

Design & development

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Evaluation board

LMK00304EVM — LMK00304 Evaluation Board

Description:

The LMK00304 Evaluation Board allows functional and performance verification of the LMK00304 high-performance 4-output differential clock buffer device.

Features:

  • Low-noise clock fan-out with two banks of two differential outputs each and one LVCMOS output
  • Selectable differential output (...)
User guide: PDF
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CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

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Simulation model

LMK00304 IBIS Model (Rev. A)

SNAM051A.ZIP (102 KB) - IBIS Model
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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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