TIDA-010132
Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132
Overview
This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is synchronized to less than 10ps skew with > 75-dB dynamic range at 2.6 GHz.
Features
- High density, scalable 8-channel RF sampling analog frontend with single FMC interface
- System clock skew less than 5 psec across devices
- Clock phase adjustment with 0.5 psec step resolution
- Low noise clock generation for 14-bit analog frontend performance
- Digital function (NCO, DDC and so forth) synchronization across multiple transceivers
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUEI5.PDF (9478 K)
Reference design overview and verified performance test data
TIDRZS5.PDF (3827 K)
Detailed schematic diagram for design layout and components
TIDRZS6.PDF (234 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRZS7.PDF (5876 K)
Detailed overview of design layout for component placement
TIDRZS9.ZIP (20489 K)
Files used for 3D models or 2D drawings of IC components
TIDCFH4.ZIP (14069 K)
Design file that contains information on physical board layer of design PCB
TIDRZS8.PDF (33501 K)
PCB layer plot file used for generating PCB design layout
Products
Includes TI products in the design and potential alternatives.
RF-sampling transceivers
AFE7444 — Quad-channel RF-sampling AFE with 14-bit 9-GSPS DAC and 3-GSPS ADC without bypass mode
Data sheetAnalog switches & muxes
SN74LVC1G3157 — 5-V, 2:1 (SPDT), 1-channel general-purpose analog switch
Data sheetAuto-direction voltage translators
TXS0102 — 2-Bit Bidirectional Voltage-Level Shifter for Open-Drain and Push-Pull Application
Data sheetClock buffers
CDCLVP1102 — Low jitter 1:2 universal-to-LVPECL buffer
Data sheetClock buffers
LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs
Data sheetClock jitter cleaners & synchronizers
LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
Data sheetClock jitter cleaners & synchronizers
LMK04832 — Ultra low-noise JESD204B compliant clock jitter cleaner with dual loop
Data sheetD-type latches
SN74LVC573A — Octal Transparent D-Type Latches With 3-State Outputs
Data sheetI2C general-purpose I/Os (GPIOs)
TCA9534A — 8-bit 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, & config registers
Data sheetInverting buffers & drivers
SN74LVC1G04 — Single 1.65-V to 5.5-V inverter
Data sheetLVDS, M-LVDS & PECL ICs
DS90LV028AQ-Q1 — Automotive LVDS dual differential line receiver
Data sheetLinear & low-dropout (LDO) regulators
LP5907 — 250-mA, low-noise, high-PSRR, ultra-low-dropout voltage regulator with low IQ and enable
Data sheetLinear & low-dropout (LDO) regulators
TPS7A47 — 1-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable
Data sheetNoninverting buffers & drivers
SN74LVC2G125 — 2-ch, 1.65-V to 5.5-V buffers with 3-state outputs
Data sheetOscillators
LMK61E2 — 156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator
Data sheetRF PLLs & synthesizers
LMX2594 — 15-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support
Data sheetStart development
Technical documentation
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| Type | Title | Date | |
|---|---|---|---|
| * | Design guide | Multichannel RF Transceiver Reference Design for Radar and Electronic Warfare | May 31, 2019 |
| User guides | Getting started with the AFE74xx RF-sampling transceiver | May 31, 2019 |
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