Multichannel RF transceiver reference design for radar and electronic warfare applications


Design files


This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is synchronized to less than 10ps skew with > 75-dB dynamic range at 2.6 GHz.

  • High density, scalable 8-channel RF sampling analog frontend with single FMC interface
  • System clock skew less than 5 psec across devices
  • Clock phase adjustment with 0.5 psec step resolution
  • Low noise clock generation for 14-bit analog frontend performance
  • Digital function (NCO, DDC and so forth) synchronization across multiple transceivers
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUEI5.PDF (9578 K)

Reference design overview and verified performance test data

TIDRZS5.PDF (3827 K)

Detailed schematic diagram for design layout and components


Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRZS7.PDF (5876 K)

Detailed overview of design layout for component placement

TIDRZS9.ZIP (20489 K)

Files used for 3D models or 2D drawings of IC components

TIDCFH4.ZIP (14069 K)

Design file that contains information on physical board layer of design PCB

TIDRZS8.PDF (33501 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

RF-sampling transceivers

AFE74444-transmit, 4-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 600-MHz IBW

Data sheet: PDF | HTML
Analog switches & muxes

SN74LVC1G31575-V, 2:1 (SPDT), 1-channel general-purpose analog switch

Data sheet: PDF | HTML
Auto-direction voltage translators

TXS01022-Bit Bidirectional Voltage-Level Shifter for Open-Drain and Push-Pull Application

Data sheet: PDF | HTML
Clock buffers

CDCLVP1102Low jitter 1:2 universal-to-LVPECL buffer

Data sheet: PDF | HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04832Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop

Data sheet: PDF | HTML
D-type latches

SN74LVC573AOctal Transparent D-Type Latches With 3-State Outputs

Data sheet: PDF
General-purpose transceivers

SN74LVC1G04Single 1.65-V to 5.5-V inverter

Data sheet: PDF
I2C general-purpose I/Os (GPIOs)

TCA9534A8-bit 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, & config registers

Data sheet: PDF | HTML

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP5907250-mA, low-noise, high-PSRR, ultra-low-dropout voltage regulator with low IQ and enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A471-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Noninverting buffers & drivers

SN74LVC2G1252-ch, 1.65-V to 5.5-V buffers with 3-state outputs

Data sheet: PDF | HTML

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML

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Technical documentation

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Type Title Date
* Design guide Multichannel RF Transceiver Reference Design for Radar and Electronic Warfare May 31, 2019
User guide Getting started with the AFE74xx RF-sampling transceiver May 31, 2019

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Reference designs

TIDA-010122 Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems TIDA-010128 Scalable 20.8 GSPS reference design for 12 bit digitizers TIDA-010131 Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01022 Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems TIDA-01028 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

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