Automotive LVDS dual differential line receiver

DS90LV028AQ-Q1

ACTIVE

Product details

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal TTL, LVTTL Rating Automotive Operating temperature range (C) -40 to 125
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal TTL, LVTTL Rating Automotive Operating temperature range (C) -40 to 125
SOIC (D) 8 19 mm² 4.9 x 3.9
  • AECQ-100 Qualified for Automotive Applications
    • Temperature Grade 1: -40°C to +125°C TA
  • >400 Mbps (200 MHz) Switching Rates
  • 50 ps Differential Skew (Typical)
  • 0.1 ns Channel-to-Channel Skew (Typical)
  • 2.5 ns Maximum Propagation Delay
  • 3.3V Power Supply Design
  • Flow-Through Pinout
  • Power Down High Impedance on LVDS Inputs
  • Low Power design (18 mW at 3.3 V static)
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Conforms to ANSI/TIA/EIA-644 Standard
  • Available in SOIC Package
  • AECQ-100 Qualified for Automotive Applications
    • Temperature Grade 1: -40°C to +125°C TA
  • >400 Mbps (200 MHz) Switching Rates
  • 50 ps Differential Skew (Typical)
  • 0.1 ns Channel-to-Channel Skew (Typical)
  • 2.5 ns Maximum Propagation Delay
  • 3.3V Power Supply Design
  • Flow-Through Pinout
  • Power Down High Impedance on LVDS Inputs
  • Low Power design (18 mW at 3.3 V static)
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Conforms to ANSI/TIA/EIA-644 Standard
  • Available in SOIC Package

The DS90LV028AQ is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028AQ has a flow-through design for easy PCB layout.

The DS90LV028AQ and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

The DS90LV028AQ is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028AQ has a flow-through design for easy PCB layout.

The DS90LV028AQ and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

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Technical documentation

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Type Title Date
* Data sheet DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver datasheet (Rev. I) 22 Jun 2020
Application note LVDS to Improve EMC in Motor Drives 27 Sep 2018
Application note How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 Aug 2018
Application note How to Terminate LVDS Connections with DC and AC Coupling 16 May 2018
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DS90LV027A-28AEVM — Dual channel LVDS driver and receiver evaluation module

The DS90LV027A-28A is an evaluation module designed for performance and functional evaluation of the Texas Instruments DS90LV027A LVDS dual  differential driver and DS90LV028A LVDS dual differential line receiver. With this kit, users can quickly evaluate the output waveform characteristics and (...)
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Simulation model

DS90LV028A IBIS Model

SNLM018.ZIP (4 KB) - IBIS Model
Simulation tool

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

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TIDA-010131 — Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers

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TIDA-01021 — Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers

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TIDA-01023 — High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
Reference designs

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This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
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SOIC (D) 8 View options

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