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Automotive LVDS dual differential line receiver

DS90LV028AQ-Q1

ACTIVE

Product details

Parameters

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal TTL, LVTTL Rating Automotive Operating temperature range (C) -40 to 125 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • AECQ-100 Qualified for Automotive Applications
    • Temperature Grade 1: -40°C to +125°C TA
  • >400 Mbps (200 MHz) Switching Rates
  • 50 ps Differential Skew (Typical)
  • 0.1 ns Channel-to-Channel Skew (Typical)
  • 2.5 ns Maximum Propagation Delay
  • 3.3V Power Supply Design
  • Flow-Through Pinout
  • Power Down High Impedance on LVDS Inputs
  • Low Power design (18 mW at 3.3 V static)
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Conforms to ANSI/TIA/EIA-644 Standard
  • Available in SOIC Package

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Description

The DS90LV028AQ is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028AQ has a flow-through design for easy PCB layout.

The DS90LV028AQ and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

open-in-new Find other LVDS, M-LVDS & PECL ICs
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NEW DS90LV028A-Q1 ACTIVE Automotive LVDS dual differential line receiver This product offers the same functionality in a 79% smaller package.

Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver datasheet (Rev. I) Jun. 22, 2020
Application note LVDS to Improve EMC in Motor Drives Sep. 27, 2018
Application note How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug. 03, 2018
Application note How to Terminate LVDS Connections with DC and AC Coupling May 16, 2018
Application note An Overview of LVDS Technology Oct. 05, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
75
Description
The DS90LV027A-28A is an evaluation module designed for performance and functional evaluation of the Texas Instruments DS90LV027A LVDS dual  differential driver and DS90LV028A LVDS dual differential line receiver. With this kit, users can quickly evaluate the output waveform characteristics and (...)
Features
  • DS90LV027A: Converts single-ended LVCMOS to differential LVDS
  • DS90LV028A: Converts differential LVDS to single-ended LVCMOS
  • Up to 400 Mbps (200 MHz) switching rates
  • Single supply operation: 3.3 V

Design tools & simulation

SIMULATION MODEL Download
SNLM018.ZIP (4 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

Reference designs

参考设计 Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
document-generic Schematic
参考设计 Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic
参考设计 Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic
参考设计 Download
Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132 — This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is (...)
document-generic Schematic
参考设计 Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic
参考设计 Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic
参考设计 Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic
参考设计 Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic
参考设计 Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic
参考设计 Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic

CAD/CAE symbols

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SOIC (D) 8 View options

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