SBASB89 May   2025 ADS117L14 , ADS117L18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Idle and Standby Modes
      3. 7.4.3 Power-Down
      4. 7.4.4 Speed Modes
      5. 7.4.5 Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6 Conversion-Start Delay Time
      7. 7.4.7 Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8 Diagnostics
        1. 7.4.8.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.8.2 SPI CRC
        3. 7.4.8.3 Register Map CRC
        4. 7.4.8.4 ADC Error
        5. 7.4.8.5 SPI Address Range
        6. 7.4.8.6 SCLK Counter
        7. 7.4.8.7 Clock Counter
        8. 7.4.8.8 Frame-Sync CRC
        9. 7.4.8.9 Self Test
      9. 7.4.9 Frame-Sync Data Port
        1. 7.4.9.1  Data Packet
        2. 7.4.9.2  Data Format
        3. 7.4.9.3  STATUS_DP Header Byte
        4. 7.4.9.4  FSYNC Pin
        5. 7.4.9.5  DCLK Pin
        6. 7.4.9.6  DOUTx Pins
        7. 7.4.9.7  DINx Pins
        8. 7.4.9.8  Time Division Multiplexing
        9. 7.4.9.9  Daisy Chain
        10. 7.4.9.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Anti-alias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Register Map

Table 8-1 lists the register memory map of the ADS117L14 and ADS117L18. Memory addresses 02h to 10h are common programming to all device channels. Addresses 11h through 30h apply to device channels 0 through 3. Addresses 31h through 50h apply to device channels 4 through 7. Unlisted register addresses are not to be written to.

Table 8-1 Register Map Summary
AddressRegisterResetBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
00hDEV_IDxxhDEV_ID[7:0]
01hREV_IDxxhREV_ID[7:0]
02hSTATUS60hRESERVEDALV_FLAGPOR_FLAGSPI_ERRREG_ERRADC_ERRADDR_ERRSCLK_ERR
03hCLK_CNT00hCLK_CNT[7:0]
04hGPIO_RD00hGPIO_RD[7:0]
05hCRC_MSB00hCRC_MSB[7:0]
06hCRC_LSB00hCRC_LSB[7:0]
07hCONTROL00hRESET[5:0]STARTSTOP
08hGEN_CFG100hRESERVEDDELAY[2:0]VCMREFP_BUFREF_RNG
09hGEN_CFG204hRESERVEDSTART_MODE[1:0]SPEED_MODE[1:0]STBY_MODE
0AhGEN_CFG3C0hOUT_DRVRESERVEDCLK_CNT_ENSPI_STAT_ENSPI_ADDR_ENSCLK_CNT_ENSPI_CRC_ENREG_CRC_EN
0BhDP_CFG120hDP_CRC_ENDP_STAT_ENDP_TDM[1:0]RESERVEDDP_DAISYRESERVED
0ChDP_CFG200hRESERVEDDCLK_DIV[1:0]DOUT_DLY[4:0]
0DhCLK_CFG00hRESERVEDCLK_SELCLK_DIV[2:0]
0EhGPIO_WR00hGPIO_WR[7:0]
0FhGPIO_DIR00hGPIO_DIR[7:0]
10hGPIO_EN00hGPIO_EN[7:0]
11hCH0_CFG100hCH0_FORMATCH0_MUX[2:0]CH0_INP_RNGCH0_EX_RNGCH0_BUFNCH0_BUFP
12hCH0_CFG200hRESERVEDCH0_PWDNCH0_FLTR[4:0]
13hCH0_OFS_MSB00hCH0_OFFSET_MSB[7:0]
14hCH0_OFS_MID00hCH0_OFFSET_MID[7:0]
15hCH0_OFS_LSB00hCH0_OFFSET_LSB[7:0]
16hCH0_GAN_MSB40hCH0_GAIN_MSB[7:0]
17hCH0_GAN_MID00hCH0_GAIN_MID[7:0]
18hCH0_GAN_LSB00hCH0_GAIN_LSB[7:0]
19hCH1_CFG100hCH1_FORMATCH1_MUX[2:0]CH1_INP_RNGCH1_EX_RNGCH1_BUFNCH1_BUFP
1AhCH1_CFG200hRESERVEDCH1_PWDNCH1_FLTR[4:0]
1BhCH1_OFS_MSB00hCH1_OFFSET_MSB[7:0]
1ChCH1_OFS_MID00hCH1_OFFSET_MID[7:0]
1DhCH1_OFS_LSB00hCH1_OFFSET_LSB[7:0]
1EhCH1_GAN_MSB40hCH1_GAIN_MSB[7:0]
1FhCH1_GAN_MID00hCH1_GAIN_MID[7:0]
20hCH1_GAN_LSB00hCH1_GAIN_LSB[7:0]
21hCH2_CFG100hCH2_FORMATCH2_MUX[2:0]CH2_INP_RNGCH2_EX_RNGCH2_BUFNCH2_BUFP
22hCH2_CFG200hRESERVEDCH2_PWDNCH2_FLTR[4:0]
23hCH2_OFS_MSB00hCH2_OFFSET_MSB[7:0]
24hCH0_OFS_MID00hCH2_OFFSET_MID[7:0]
25hCH2_OFS_LSB00hCH2_OFFSET_LSB[7:0]
26hCH2_GAN_MSB40hCH2_GAIN_MSB[7:0]
27hCH2_GAN_MID00hCH2_GAIN_MID[7:0]
28hCH2_GAN_LSB00hCH2_GAIN_LSB[7:0]
29hCH3_CFG100hCH3_FORMATCH3_MUX[2:0]CH3_INP_RNGCH3_EX_RNGCH3_BUFNCH3_BUFP
2AhCH3_CFG200hRESERVEDCH3_PWDNCH3_FLTR[4:0]
2BhCH3_OFS_MSB00hCH3_OFFSET_MSB[7:0]
2ChCH3_OFS_MID00hCH3_OFFSET_MID[7:0]
2DhCH3_OFS_LSB00hCH3_OFFSET_LSB[7:0]
2EhCH3_GAN_MSB40hCH3_GAIN_MSB[7:0]
2FhCH3_GAN_MID00hCH3_GAIN_MID[7:0]
30hCH3_GAN_LSB00hCH3_GAIN_LSB[7:0]
31hCH4_CFG100hCH4_FORMATCH4_MUX[2:0]CH4_INP_RNGCH4_EX_RNGCH4_BUFNCH4_BUFP
32hCH4_CFG200hRESERVEDCH4_PWDNCH4_FLTR[4:0]
33hCH4_OFS_MSB00hCH4_OFFSET_MSB[7:0]
34hCH4_OFS_MID00hCH4_OFFSET_MID[7:0]
35hCH4_OFS_LSB00hCH4_OFFSET_LSB[7:0]
36hCH4_GAN_MSB40hCH4_GAIN_MSB[7:0]
37hCH4_GAN_MID00hCH4_GAIN_MID[7:0]
38hCH4_GAN_LSB00hCH4_GAIN_LSB[7:0]
39hCH5_CFG100hCH5_FORMATCH5_MUX[2:0]CH5_INP_RNGCH5_EX_RNGCH5_BUFNCH5_BUFP
3AhCH5_CFG200hRESERVEDCH5_PWDNCH5_FLTR[4:0]
3BhCH5_OFS_MSB00hCH5_OFFSET_MSB[7:0]
3ChCH5_OFS_MID00hCH5_OFFSET_MID[7:0]
3DhCH5_OFS_LSB00hCH5_OFFSET_LSB[7:0]
3EhCH5_GAN_MSB40hCH5_GAIN_MSB[7:0]
3FhCH5_GAN_MID00hCH5_GAIN_MID[7:0]
40hCH5_GAN_LSB00hCH5_GAIN_LSB[7:0]
41hCH6_CFG100hCH6_FORMATCH6_MUX[2:0]CH6_INP_RNGCH6_EX_RNGCH6_BUFNCH6_BUFP
42hCH6_CFG200hRESERVEDCH6_PWDNCH6_FLTR[4:0]
43hCH6_OFS_MSB00hCH6_OFFSET_MSB[7:0]
44hCH6_OFS_MID00hCH6_OFFSET_MID[7:0]
45hCH6_OFS_LSB00hCH6_OFFSET_LSB[7:0]
46hCH6_GAN_MSB40hCH6_GAIN_MSB[7:0]
47hCH6_GAN_MID00hCH6_GAIN_MID[7:0]
48hCH6_GAN_LSB00hCH6_GAIN_LSB[7:0]
49hCH7_CFG100hCH7_FORMATCH7_MUX[2:0]CH7_INP_RNGCH7_EX_RNGCH7_BUFNCH7_BUFP
4AhCH7_CFG200hRESERVEDCH7_PWDNCH7_FLTR[4:0]
4BhCH7_OFS_MSB00hCH7_OFFSET_MSB[7:0]
4ChCH7_OFS_MID00hCH7_OFFSET_MID[7:0]
4DhCH7_OFS_LSB00hCH7_OFFSET_LSB[7:0]
4EhCH7_GAN_MSB40hCH7_GAIN_MSB[7:0]
4FhCH7_GAN_MID00hCH7_GAIN_MID[7:0]
50hCH7_GAN_LSB00hCH7_GAIN_LSB[7:0]

Table 8-2 shows the access-type codes in this section.

Table 8-2 Register Access-Type Codes
Access TypeCodeDescription
RRRead only
WWWrite only
W1CW1CWrite 1 to clear
R/WR/WRead or write

8.1 DEV_ID Register (Address = 00h) [Reset = 04h or 06h]

DEV_ID is described in Table 8-3.

Table 8-3 DEV_ID Register Description
BitFieldTypeResetDescription
7-0DEV_ID[7:0]R00000xx0bDevice identification number.
00000101b = ADS117L14
00000111b = ADS117L18

8.2 REV_ID Register (Address = 01h) [Reset = xxh]

REV_ID is described in Table 8-4.

Table 8-4 REV_ID Register Description
BitFieldTypeResetDescription
7-0REV_ID[7:0]RxxxxxxxxbDie revision number.
The die revision number is subject to change during device production without prior notice.

8.3 STATUS Register (Address = 02h) [Reset = 60h]

STATUS is shown in Figure 8-51 and described in Table 8-23.

Figure 8-1 STATUS Register
76543210
RESERVEDALV_FLAGPOR_FLAGSPI_ERRREG_ERRADC_ERRADDR_ERRSCLK_ERR
R-0bR/W1C-1bR/W1C-1bR/W1C-0bR/W1C-0bR-0bR/W1C-0bR/W1C-0b
Table 8-5 STATUS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved
6ALV_FLAGR/W1C1bAnalog supply low-voltage flag.
This bit indicates a low-voltage condition of the analog power supplies. Write 1b to reset the flag to detect the next occurrence of a low-voltage condition.
0b = No event from when flag last cleared
1b = Analog power supply low-voltage detected
5POR_FLAGR/W1C1bPower-on reset flag.
This bit indicates the device was reset at power-on or brownout of the IOVDD power supply or by a user reset operation. Write 1b to reset the flag to detect the next occurrence of a device reset.
0b = No reset from when flag last cleared
1b = Reset occurred
4SPI_ERRR/W1C0bSPI CRC error.
This bit indicates an SPI CRC error was detected. Except for this register, register write operations are blocked when the bit is set. Clear the bit by writing 1b. CRC validation is enabled by the SPI_CRC_EN bit.
0b = No error
1b = SPI CRC error
3REG_ERRR/W1C0bRegister map CRC error.
This bit indicates a register map CRC error. The user writes a 16-bit CRC value to the CRC_MSB and CRC_LSB registers, calculated over addresses 08h to 50h for both devices. Clear the error by correcting the CRC value, then write 1b to clear the bit. The register map CRC validation is enabled by the REG_CRC_EN register bit.
0b = No error
1b = Register map CRC error
2ADC_ERRR0bADC error.
This bit indicates an internal ADC error. Reset the device or perform a power cycle to clear the error.
0b = No error
1b = ADC error
1ADDR_ERRR/W1C0bSPI register address error.
This bit indicates an invalid register read or write address. The valid address range is 00h to 50h for both devices. Except for the STATUS register, register write operations are blocked when the error is set. Clear the error by writing 1b. Address error check is enabled by setting SPI_ADDR_EN = 1b.
0b = No error
1b = Invalid register read/write address
0SCLK_ERRR/W1C0bSPI SCLK count error.
This bit indicates the number of SCLK cycles was not a multiple of eight. Except for the STATUS register, register write operations are blocked when the flag is set. Clear the error by writing 1b. SCLK count error check is enabled by setting SCLK_CNT_EN = 1b.
0b = No error
1b = Number of SCLK clock cycles is not a multiple of eight

8.4 CLK_CNT Register (Address = 03h) [Reset = 00h]

CLK_CNT is described in Table 8-6.

Table 8-6 CLK_CNT Register Description
BitFieldTypeResetDescription
7-0CLK_CNT[7:0]R00000000bClock count value register.
This register is a counter of the ADC clock. The counter increments at a rate of fCLK / 32, divided by the CLK_DIV[2:0] setting. Read the register at known intervals to verify the ADC clock frequency. The clock count is enabled by the CLK_CNT_EN register bit. When enabled, the counter value resets to 00h. When disabled, the count value is 00h.

8.5 GPIO_RD Register (Address = 04h) [Reset = 00h]

GPIO_RD is shown in Figure 8-2 and described in Table 8-7.

Figure 8-2 GPIO_RD Register
76543210
GPIO_RD7GPIO_RD6GPIO_RD5GPIO_RD4GPIO_RD3GPIO_RD2GPIO_RD1GPIO_RD0
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 8-7 GPIO_RD Register Field Descriptions
BitFieldTypeResetDescription
7-0GPIO_RD[7:0]R00000000bGPIO read data register.
These bits are the read values of GPIO. If the GPIO is programmed as an output, the value returned is from the GPIO pin.

8.6 CRC_MSB, CRC_LSB Registers (Addresses = 05h, 06h) [Reset = 00h]

CRC registers described in Table 8-8.

Table 8-8 CRC Registers Description
NameAddressTypeResetDescription
CRC_MSB
CRC_LSB		5h
6h		R/W
R/W		00h
00h		Two-byte register map CRC value.
Write a 16-bit CRC value, computed over the register range 08h to 50h. The register map CRC check is enabled by the REG_CRC_EN bit. The CRC error is reported to the REG_ERR bit of the STATUS register.

8.7 CONTROL Register (Address = 07h) [Reset = 00h]

CONTROL is shown in Figure 8-3 and described in Table 8-9.

Figure 8-3 CONTROL Register
76543210
RESET[5:0]STARTSTOP
R/W-000000bR/W-0bR/W-0b
Table 8-9 CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-2RESET[5:0]R/W000000bSoftware reset.
Write the value of 010110b to reset the ADC. Make sure the START or STOP bits are also 0b in the same write operation. These bits self-clear and always read 000000b.
1STARTR/W0bSTART conversions.
Start channel conversions by writing 1b. This bit also restarts an ongoing conversion. Conversions continue until 1b is written to the STOP bit. This bit self-clears after written, therefore always reads 0b. This bit is not functional in synchronized control mode.
0b = No operation
1b = Start or restart conversions
0STOPR/W0bStop conversions.
Stop channel conversions by writing 1b. This bit self-clears after written, therefore always reads 0b. This bit is not functional in synchronized control mode.
0b = No operation
1b = Stop conversions on all channels

8.8 GEN_CFG1 Register (Address = 08h) [Reset = 00h]

GEN_CFG1 is shown in Figure 8-4 and described in Table 8-10.

Figure 8-4 GEN_CFG1 Register
7654321
RESERVEDDELAY[2:0]VCMREFP_BUFREF_RNG
R-00bR/W-000bR/W-0bR/W-0bR/W-0b
Table 8-10 GEN_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved.
5-3DELAY[2:0]R/W000bConversion start delay time selection.
Select the conversion start delay time in number of fMOD cycles after taking START high (or setting the START bit).
000b = 0
001b = 4
010b = 8
011b = 16
100b = 32
101b = 128
110b = 512
111b = 1024
2VCMR/W0bCommon-mode voltage output enable.
This bit enables the common-mode voltage output of the VCM pin. The VCM output voltage is equal to (AVDD1 + AVSS) / 2.
0b = Disabled
1b = Enabled
1REFP_BUFR/W0bReference positive buffer enable.
This bit enables the REFP precharge buffers for all channels.
0b = Disabled
1b = Enabled
0REF_RNGR/W0bVoltage reference range selection.
This bit selects the low or high voltage operating range of the reference input. Program the range to match the actual reference voltage.
0b = Low-voltage reference range
1b = High-voltage reference range

8.9 GEN_CFG2 Register (Address = 09h) [Reset = 04h]

GEN_CFG2 is shown in Figure 8-5 and described in Table 8-11.

Figure 8-5 GEN_CFG2 Register
76543210
RESERVEDSTART_MODE[1:0]SPEED_MODE[1:0]STBY_MODE
R-000bR/W-00bR/W-10bR/W-0b
Table 8-11 GEN_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR000bReserved
4-3START_MODE[1:0]R/W00bSTART mode selection.
These bits program the functional mode of the START pin. See the Synchronization section for more details.
00b = Start/stop control mode
01b = Reserved
10b = Synchronized control mode
11b = Reserved
2-1SPEED_MODE[1:0]R/W10bSpeed mode selection.
These bits program the device speed mode.
00b = Low-speed mode (fCLK = 3.2MHz)
01b = Mid-speed mode (fCLK = 12.8MHz)
10b = High-speed mode (fCLK = 25.6MHz)
11b = Max-speed mode (fCLK = 32.768MHz)
0STBY_MODER/W0bStandby mode selection.
This bit enables the standby mode when conversions are stopped. Standby mode reduces power consumption compared to the idle mode.
0b = Idle mode, device fully powered
1b = Standby mode, analog section of channels powered down

8.10 GEN_CFG3 Register (Address = 0Ah) [Reset = 80h]

GEN_CFG3 is shown in Figure 8-6 and described in Table 8-12.

Figure 8-6 GEN_CFG3 Register
76543210
OUT_DRVRESERVEDCLK_CNT_ENSPI_STAT_ENSPI_ADDR_ENSCLK_CNT_ENSPI_CRC_ENREG_CRC_EN
R/W-1bR-1bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-12 GEN_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7OUT_DRVR/W1bDigital output drive selection.
Select the digital output driver strength. Full drive strength increases the slew rate of the output signal.
0b = Full-power driver strength
1b = Half-power driver strength
6RESERVEDR1bReserved
5CLK_CNT_ENR/W0bClock counter enable.
This bit enables the ADC clock counter register.
0b = Disabled
1b = Enabled
4SPI_STAT_ENR/W0bSPI status byte output enable.
This bit enables the STATUS register value in the SPI output.
0b = Disabled
1b = Enabled
3SPI_ADDR_ENR/W0bSPI register address enable.
This bit enables the SPI address verification. The ADDR_ERR bit of the STATUS register sets if the register read or write address is invalid.
0b = Disabled
1b = Enabled
2SCLK_CNT_ENR/W0bSCLK count enable.
This bit enables the SPI SCLK count verification. The SCLK_ERR bit of the STATUS register sets if the number of SCLK cycles in a frame are not multiples of 8.
0b = Disabled
1b = Enabled
1SPI_CRC_ENR/W0bSPI CRC enable.
This bit enables the SPI CRC output byte and the input data CRC check. The SPI_ERR bit of the STATUS byte sets if the input CRC is in error. Write 1b to the SPI_ERR bit to clear the error.
0b = Disabled
1b = Enabled
0REG_CRC_ENR/W0bRegister map CRC enable.
This bit enables the register map CRC error verification. The REG_ERR bit of the STATUS byte sets if the CRC value is not correct.
0b = Disabled
1b = Enabled

DP_CFG1 Register (Address = 0Bh) [Reset = 20h]

DP_CFG1 is shown in Figure 8-7 and described in Table 8-13.

Figure 8-7 DP_CFG1 Register
76543210
DP_CRC_ENDP_STAT_ENDP_TDM[1:0]RESERVEDDP_DAISYRESERVED
R/W-0bR/W-0bR/W-10bR-00bR/W-0bR-0b
Table 8-13 DP_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7DP_CRC_ENR/W0bData port CRC byte enable.
This bit enables the data port CRC byte. A CRC byte is appended to the end of the channel data.
0b = Disabled
1b = Enabled
6DP_STAT_ENR/W0bData port status byte enable.
This bit enables the data port status byte. The status byte is prefixed to the beginning of the channel data.
0b = Disabled
1b = Enabled
5-4DP_TDM[1:0]R/W10bData port time division multiplexing (TDM) configuration.
These bits select the number of data lanes. See the Time Division Multiplexing section for details.
00b = One data lane
01b = One (ADS117L14) / two data lanes (ADS117L18)
10b = Two (ADS117L14) / four data lanes (ADS117L18)
11b = Four (ADS117L14) / eight data lanes (ADS117L18)
3-2RESERVEDR00bReserved.
1DP_DAISYR/W0bData port daisy-chain mode.
This bit selects daisy-chain or repeat data modes.
0b = TDM data mode. DINx data are shifted-in and appended to the original channel data.
1b = Repeat data mode. Original channel data are repeated and DINx data are ignored.
0RESERVEDR0bReserved.

8.11 DP_CFG2 Register (Address = 0Ch) [Reset = 00h]

DP_CFG2 is shown in Figure 8-8 and described in Table 8-14.

Figure 8-8 DP_CFG2 Register
76543210
RESERVEDDCLK_DIV[1:0]DOUT_DLY[4:0]
R-0bR/W-00bR/W-00000b
Table 8-14 DP_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved
6-5DCLK_DIV[1:0]R/W00bData port DCLK frequency divider.
These bits select the frame-sync DCLK frequency.
00b = Divide by 1
01b = Divide by 2
10b = Divide by 4
11b = Divide by 8
4-0DOUT_DLY[4:0]R/W00000bData port DOUTx delay.
These bits select the delay or advance of the DOUTx signals relative to the DCLK and FSYNC signals. Positive values advance the DOUTx signals; negative values delay the DOUTx signals. The bit weight is approximately 0.3ns. See the Data Port Offset Timing section for details.

8.12 CLK_CFG Register (Address = 0Dh) [Reset = 00h]

CLK_CFG is shown in Figure 8-9 and described in Table 8-15.

Figure 8-9 CLK_CFG Register
76543210
RESERVEDCLK_SELCLK_DIV[2:0]
R-0000bR/W-0bR/W-000b
Table 8-15 CLK_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0000bReserved.
3CLK_SELR/W0bADC clock selection.
This bit selects the internal oscillator or external clock operation.
0b = Internal oscillator
1b = External clock
2-0CLK_DIV[2:0]R/W000bADC clock divider.
These bits select the clock signal divider for both external clock and internal oscillator.
000b = Divide by 1
001b = Divide by 2
010b = Divide by 3
011b = Divide by 4
100b - 111b = Divide by 8

8.13 GPIO_WR Register (Address = 0Eh) [Reset = 00h]

GPIO_WR is shown in Figure 8-10 and described in Table 8-16.

Figure 8-10 GPIO_WR Register
76543210
GPIO_WR7GPIO_WR6GPIO_WR5GPIO_WR4GPIO_WR3GPIO_WR2GPIO_WR1GPIO_WR0
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-16 GPIO_WR Register Field Descriptions
BitFieldTypeResetDescription
7-0GPIO_WR[7:0]R/W00000000bGPIO write data.
This register is the GPIO write data register. Set the direction of the GPIO pins to output mode to write the value. See the GPIO_RD register to read GPIO data.
0b = GPIO pin is driven low
1b = GPIO pin is driven high

8.14 GPIO_DIR Register (Address = 0Fh) [Reset = 00h]

GPIO_DIR is shown in Figure 8-11 and described in Table 8-17.

Figure 8-11 GPIO_DIR Register
76543210
GPIO_DIR7GPIO_DIR6GPIO_DRI5GPIO_DIR4GPIO_DIR3GPIO_DIR2GPIO_DIR1GPIO_DIR0
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-17 GPIO_DIR Register Field Descriptions
BitFieldTypeResetDescription
7-0GPIO_DIR[7:0]R/W00000000bGPIO direction.
This register programs the GPIO direction as inputs or outputs.
0b = The GPIO pin is an output
1b = The GPIO pin is an input

8.15 GPIO_EN Register (Address = 10h) [Reset = 00h]

GPIO_EN is shown in Figure 8-12 and described in Table 8-18.

Figure 8-12 GPIO_EN Register
76543210
GPIO_EN7GPIO_EN6GPIO_EN5GPIO_EN4GPIO_EN3GPIO_EN2GPIO_EN1GPIO_EN0
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-18 GPIO_EN Register Field Descriptions
BitFieldTypeResetDescription
7-0GPIO_EN[7:0]R/W00000000bGPIO enable.
This register enables the GPIO function for each pin. When enabled, the GPIO pin function has priority over other pin functions.
0b = GPIO pin is disabled
1b = GPIO pin is enabled

8.16 CHn_CFG1 Registers (Address = Channel Number × 08h + 11h) [Reset = 00h]

Channel n configuration 1 register addresses are shown in Table 8-19. The register bit map is shown in Figure 8-13 and described in Table 8-20.

Table 8-19 CHn_CFG1 Register Addresses
NAMEDESCRIPTIONADDRESS
CH0_CFG1Channel 0 configuration 111h
CH1_CFG1Channel 1 configuration 119h
CH2_CFG1Channel 2 configuration 121h
CH3_CFG1Channel 3 configuration 129h
CH4_CFG1Channel 4 configuration 131h
CH5_CFG1Channel 5 configuration 139h
CH6_CFG1Channel 6 configuration 141h
CH7_CFG1Channel 7 configuration 149h
Figure 8-13 CHn_CFG1 Register
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CHn_FORMATCHn_MUX[2:0]CHn_INP_RNGCHn_EX_RNGCHn_BUFNCHn_BUFP
R/W-0bR/W-000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-20 CHn_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7CHn_FORMATR/W0bData Format.
This bit selects the data format.
0b = Two's complement format for positive and negative signals
1b = Straight binary format for positive signals only
6-4CHn_MUX[2:0]R/W000bChannel input multiplexer selection.
These bits select between the signal input or input test modes. See the Analog Inputs (AINP, AINN) section for details.
000b = Normal input polarity
001b = Reverse input polarity
010b = Offset and noise test: Internal short to mid supply
011b = CMRR test to AINP
100b = CMRR test to AINN
101b = –FS test
110b = +FS test
111b = +FS test
3CHn_INP_RNGR/W0bChannel input range selection.
This bit selects the 1x or 2x input range. See the Input Range section for more details.
0b = 1x input range
1b = 2x input range
2CHn_EX_RNGR/W0bChannel extended input range selection.
This bit extends the input range by 25%. See the Input Range section for more details.
0b = Disabled
1b = Enabled: The FS range is extended by 25%
1CHn_BUFNR/W0bChannel analog input negative buffer enable.
This bit enables the channel AINN precharge buffer.
0b = Disabled
1b = Enabled
0CHn_BUFPR/W0bChannel analog input positive buffer enable.
This bit enables the channel AINP precharge buffer.
0b = Disabled
1b = Enabled

8.17 CHn_CFG2 Registers (Address = Channel Number × 08h + 12h) [Reset = 00h]

Channel n configuration 2 register addresses are shown in Table 8-21. The register bit map is shown in Figure 8-14 and described in Table 8-22.

Table 8-21 CHn_CFG2 Register Addresses
NAMEREGISTER DESCRIPTIONADDRESS
CH0_CFG2Channel 0 configuration 212h
CH1_CFG2Channel 1 configuration 21Ah
CH2_CFG2Channel 2 configuration 222h
CH3_CFG2Channel 3 configuration 22Ah
CH4_CFG2Channel 4 configuration 232h
CH5_CFG2Channel 5 configuration 23Ah
CH6_CFG2Channel 6 configuration 242h
CH7_CFG2Channel 7 configuration 24Ah
Figure 8-14 CHn_CFG2 Register
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RESERVEDCHn_PWDNCHn_FLTR[4:0]
R-00bR/W-0bR/W-00000b
Table 8-22 CHn_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved.
5CHn_PWDNR/W0bChannel power-down mode selection.
When set, the ADC channel is powered down. When powered down, channel data are the last remaining data.
0b = Active
1b = Powered down
4-0CHn_FLTR[4:0]R/W00000bChannel digital filter and data rate selection.
These bits configure the digital filter and data rate for each channel. The data rate between channels must be related by power of 2. The device has five filter configurations: wideband, sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1. See the Digital Filter section for the data rate corresponding to the OSR.
00000b = Wideband: OSR = 32
00001b = Wideband: OSR = 64
00010b = Wideband: OSR = 128
00011b = Wideband: OSR = 256
00100b = Wideband: OSR = 512
00101b = Wideband: OSR = 1024
00110b = Wideband: OSR = 2048
00111b = Wideband: OSR = 4096
01000b = Sinc4: OSR = 12
01001b = Sinc4: OSR = 16
01010b = Sinc4: OSR = 24
01011b = Sinc4: OSR = 32
01100b = Sinc4: OSR = 64
01101b = Sinc4: OSR = 128
01110b = Sinc4: OSR = 256
01111b = Sinc4: OSR = 512
10000b = Sinc4: OSR = 1024
10001b = Sinc4: OSR = 2048
10010b = Sinc4: OSR = 4096
10011b = Sinc4: OSR = 32 + sinc1: OSR = 2
10100b = Sinc4: OSR = 32 + sinc1: OSR = 4
10101b = Sinc4: OSR = 32 + sinc1: OSR = 10
10110b = Sinc4: OSR = 32 + sinc1: OSR = 20
10111b = Sinc4: OSR = 32 + sinc1: OSR = 40
11000b = Sinc4: OSR = 32 + sinc1: OSR = 100
11001b = Sinc4: OSR = 32 + sinc1: OSR = 200
11010b = Sinc4: OSR = 32 + sinc1: OSR = 400
11011b = Sinc4: OSR = 32 + sinc1: OSR = 1000
11100b = Sinc3: OSR = 26667
11101b = Sinc3: OSR = 32000
11110b = Sinc3: OSR = 32000 + sinc1: OSR = 3
11111b = Sinc3: OSR = 32000 + sinc1: OSR = 5

8.18 CHn Offset Registers [Reset = 000000h]

Channel n offset registers are described in Table 8-23.

Table 8-23 CHn Offset Registers Description
NAMEADDRESSTYPERESETDESCRIPTION
MSBMIDLSB
Channel 0 offset13h14h15hR/W000000hThree-byte offset word.
Three registers form the 24-bit offset calibration word for each channel. The offset value is in two's-complement representation and is subtracted from the conversion result. The offset operation precedes the gain operation. Conversion data are left-justified to align with the offset value.
Channel 1 offset1Bh1Ch1Dh
Channel 2 offset23h24h25h
Channel 3 offset2Bh2Ch2Dh
Channel 4 offset33h34h35h
Channel 5 offset3Bh3Ch3Dh
Channel 6 offset43h44h45h
Channel 7 offset4Bh4Ch4Dh

8.19 CHn Gain Registers [Reset = 400000h]

Channel n gain registers are described in Table 8-24.

Table 8-24 CHn Gain Registers Description
NAMEADDRESSTYPERESETDESCRIPTION
MSBMIDLSB
Channel 0 gain16h17h18hR/W400000hThese registers are three-byte gain registers.
Three registers form the 24-bit gain calibration word of each channel. The gain value is in straight-binary representation and is normalized to 400000h for gain = 1. The conversion data are multiplied by GAIN[23:0] / 400000h after the offset operation.
Channel 1 gain1Eh1Fh20h
Channel 2 gain26h27h28h
Channel 3 gain2Eh2Fh30h
Channel 4 gain36h37h38h
Channel 5 gain3Eh3Fh40h
Channel 6 gain46h47h48h
Channel 7 gain4Eh4Fh50h