SLVSHO1A March 2025 – December 2025 TPS1689
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The TPS1689 implements all PMBus® status registers relevant to an eFuse/Hot-swap power controller. Figure 7-16 shows a bit map of the TPS1689 status register.
STATUS_BYTE is a standard PMBus® command that returns one byte of information with a summary of the most critical faults.
This command uses the PMBus® read byte protocol.
To clear bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must be issued by the host controller.
| Bit | Name | Value | Description | Default | Live/Latched | Access |
|---|---|---|---|---|---|---|
7 | BUSY | Device busy status | Read | |||
1 | Device is busy | 0 | Live | |||
0 | Device is not busy | |||||
6 | FET_OFF | FET drive status | ||||
1 | FET gate driver disabled | 0 | Live | |||
0 | FET gate drive enabled | |||||
5:4 | Reserved | 00 | Reserved | 00 | ||
3 | VIN_UV_FLT | VIN undervoltage | ||||
1 | VIN UV fault detected | 0 | Latched | |||
0 | VIN UV fault not detected | |||||
2 | STATUS_TEMP | Overtemperature fault | ||||
1 | Active bits set in STATUS_TEMP register | 0 | Live | |||
0 | No active bits set in STATUS_TEMP register | |||||
1 | CML_ERR | Communication, Memory or Logic error | ||||
1 | Active bits set in STATUS_CML register | 0 | Live | |||
0 | No active bits set in STATUS_CML register | |||||
0 | NONE_OF_THE_ABOVE | 1 | An event other than the ones listed in bits 7:1 has occurred | 0 | Live | |
0 | An event other than the ones listed in bits 7:1 has not occurred |