SLVSHO1A March 2025 – December 2025 TPS1689
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| GPIOx | ||||||
| VOL | GPIOx output logic low | Pin configured as output, de-asserted Low. Sink current = 20mA. | 0.27 | V | ||
| VOH | GPIOx output logic high | Pin configured as output, asserted high | 1.7 | V | ||
| RGPIO | GPIOx pin pull-down resistance | Pin configured as output, de-asserted Low | 13 | Ω | ||
| IGPIO | GPIOx pin leakage current | Pin configured as output, asserted high | 1 | uA | ||
| VIH | GPIOx input logic high | Pin configured as input | 1.6 | V | ||
| VIL | GPIOx input logic low | Pin configured as input | 0.75 | V | ||
| PMBus (SCL/SDA) | ||||||
| ILK-PMB-BUS | Input leakage per PMBus segment | -200 | 200 | µA | ||
| ILK-PMB-PIN | Input leakage for PMBus pins - SCL | -1.5 | 1 | µA | ||
| ILK-PMB-PIN | Input leakage for PMBus pins - SDA | -1.5 | 1 | µA | ||
| VPULLUP_PMBus | PMBus interface pull ups | 1.62 | 3.63 | V | ||
| VIL_PMBus | SDA Input logic low | 0.8 | V | |||
| VIL_PMBus | SCL Input logic low | 0.8 | V | |||
| VIH_PMBus | SCL Input logic high | 1.35 | V | |||
| VIH_PMBus | SDA Input logic high | 1.35 | V | |||
| VHYST_PMBus | Hysteresis voltage SCL | 80 | mV | |||
| VHYST_PMBus | Hysteresis voltage SDA | 80 | mV | |||
| VOL_PMBus | Low-level output voltage - SCL | IOL = -20 mA | 0.4 | V | ||
| VOL_PMBus | Low-level output voltage - SDA | IOL = -20 mA | 0.4 | V | ||