SBASAE3 December   2025 ADS125H18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Divider and Input Multiplexer
      2. 7.3.2  Input Range
      3. 7.3.3  ADC Reference Voltage
      4. 7.3.4  Power Supplies
        1. 7.3.4.1 AVDD and AVSS
        2. 7.3.4.2 IOVDD
        3. 7.3.4.3 CAPA and CAPD
        4. 7.3.4.4 Power-On Reset (POR)
      5. 7.3.5  Clock Operation
        1. 7.3.5.1 Internal Oscillator
        2. 7.3.5.2 External Clock
      6. 7.3.6  Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Digital Filter Latency
        2. 7.3.7.2 Sinc3 and Sinc4 Filters
        3. 7.3.7.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.7.4 50/60Hz Notch Filters
      8. 7.3.8  FIFO Buffer
        1. 7.3.8.1 FIFO Buffer Read and Write
        2. 7.3.8.2 FIFO Overflow and Underflow
        3. 7.3.8.3 FIFO Depth Indicator
        4. 7.3.8.4 FIFO Enable and Flush
        5. 7.3.8.5 FIFO Thresholds
      9. 7.3.9  Channel Auto-Sequencer
        1. 7.3.9.1 Auto-Sequencer: Basic Operation
        2. 7.3.9.2 Sequencer Modes
          1. 7.3.9.2.1 Single-Shot Mode
          2. 7.3.9.2.2 Single Step Continuous Conversion Mode
          3. 7.3.9.2.3 Single Sequence Mode
          4. 7.3.9.2.4 Continuous Sequence Mode
        3. 7.3.9.3 Configuring the Auto-Sequencer
        4. 7.3.9.4 Starting and Stopping the Sequencer
        5. 7.3.9.5 Auto-Sequencer and DRDY Behavior
      10. 7.3.10 Offset and Gain Calibration
      11. 7.3.11 Digital PGA
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Open Wire Current Source (OWCS)
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
        5. 7.3.15.5 Resistor Divider Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125H18 Status and General Configuration Page
      2. 7.6.2 ADS125H18 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Applications
      1. 8.2.1 2-Terminal V/I PLC Analog Input Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots - Crosstalk
      2. 8.2.2 3-Terminal V/I PLC Analog Input Module
      3. 8.2.3 2 -Terminal V/I PLC Analog Input Module With Solid State Switch
      4. 8.2.4 2-Terminal, single ended V/I PLC Analog Input Module
      5. 8.2.5 2-Terminal, I-Input PLC Analog Input Module
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6.2 ADS125H18 Step Configuration Page

Table 7-92 lists the memory-mapped registers for the ADS125H18 Step Configuration Page registers. All register offset addresses not listed in Table 7-92 should be considered as reserved locations and the register contents should not be modified.

Table 7-92 Register Map
AddressAcronymResetBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
00hSTEPx_AIN_CFG00hRESERVEDSTEPx_AIN[4:0]
01hRESERVED00hRESERVEDRESERVED
02hSTEPx_ADC_REF_CFG00hSTEPx_GAIN_BIN[1:0]STEPx_CODINGSTEPx_REF_SELSTEPx_NUM_CONV[3:0]
03hSTEPx_FLTR1_CFG01hRESERVEDSTEPx_FLTR_MODESTEPx_FLTR_OSR[4:0]
04hSTEPx_DELAY_MSB_CFG00hSTEPx_DELAY_MSB[7:0]
05hSTEPx_DELAY_LSB_CFG00hSTEPx_DELAY_LSB[7:0]
06hSTEPx_OFFSET_CAL_MSB00hSTEPx_OFFSET_CAL[23:16]
07hSTEPx_OFFSET_CAL_ISB00hSTEPx_OFFSET_CAL[15:8]
08hSTEPx_OFFSET_CAL_LSB00hSTEPx_OFFSET_CAL[7:0]
09hSTEPx_GAIN_CAL_MSB40hSTEPx_GAIN_CAL[15:8]
0AhSTEPx_GAIN_CAL_LSB00hSTEPx_GAIN_CAL[7:0]
0BhSTEPx_OW_SYSMON_CFG00hRESERVEDSTEPx_OWCS_ENRESERVEDSTEPx_SYS_MON[3:0]
0ChSTEPx_TDAC_CFG000hRESERVEDSTEPx_TDAC_VAL[4:0]
0DhSTEPx_TDAC_CFG100hRESERVEDSTEPx_TDAC_SEL[4:0]
0EhSTEPx_SPARE_CFG00hSTEPx_SPARE7STEPx_SPARE6STEPx_SPARE5STEPx_SPARE4STEPx_SPARE3STEPx_SPARE2STEPx_SPARE1STEPx_SPARE0
0FhRESERVED00hRESERVEDRESERVED
10hSTEPx_GPIO_DATA_OUT00hRESERVEDSTEPx_GPIO3_DAT_OUTSTEPx_GPIO2_DAT_OUTSTEPx_GPIO1_DAT_OUTSTEPx_GPIO0_DAT_OUT
3DhSTEPx_REG_MAP_CRC00hSTEPx_REG_MAP_CRC_VALUE[7:0]
3EhSTEPx_PAGE_INDICATOR00hSTEPx_PAGE_INDICATOR[7:0]
3FhSTEPx_PAGE_POINTER00hSTEPx_PAGE_POINTER[7:0]

Complex bit access types are encoded to fit into small table cells. Table 7-93 shows the codes that are used for access types in this section.

Table 7-93 ADS125H18 Step Configuration Page Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.2.1 STEPx_AIN_CFG Register (Address = 00h) [Reset = 00h]

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Figure 7-113 STEPx_AIN_CFG Register
76543210
RESERVEDSTEPx_AIN[4:0]
R-000bR/W-00000b
Table 7-94 STEPx_AIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR000bReserved
Always reads 000b
4:0STEPx_AIN[4:0]R/W00000bMultiplexer input selection
Selects the analog input for the ADC. This register is ignored if system monitors are active.
  • 00000b = (AIN0-RESN)
  • 00001b = (AIN1-RESN)
  • 00010b = (AIN2-RESN)
  • 00011b = (AIN3-RESN)
  • 00100b = (AIN4-RESN)
  • 00101b = (AIN5-RESN)
  • 00110b = (AIN6-RESN)
  • 00111b = (AIN7-RESN)
  • 01000b = (AIN8-RESN)
  • 01001b = (AIN9-RESN)
  • 01010b = (AIN10-RESN)
  • 01011b = (AIN11-RESN)
  • 01100b = (AIN12-RESN)
  • 01101b = (AIN13-RESN)
  • 01110b = (AIN14-RESN)
  • 01111b = (AIN15-RESN)
  • 10000b = (AIN0-AIN1)
  • 10001b = (AIN2-AIN3)
  • 10010b = (AIN4-AIN5)
  • 10011b = (AIN6-AIN7)
  • 10100b = (AIN8-AIN9)
  • 10101b = (AIN10-AIN11)
  • 10110b = (AIN12-AIN13)
  • 10111b = (AIN14-AIN15)
  • 11000b = Open
  • 11001b = Open
  • 11010b = Open
  • 11011b = Open
  • 11100b = Open
  • 11101b = Open
  • 11110b = Open
  • 11111b = Open

7.6.2.2 STEPx_ADC_REF_CFG Register (Address = 02h) [Reset = 00h]

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Figure 7-114 STEPx_ADC_REF_CFG Register
76543210
STEPx_GAIN_BIN[1:0]STEPx_CODINGSTEPx_REF_SELSTEPx_NUM_CONV[3:0]
R/W-00bR/W-0bR/W-0bR/W-0000b
Table 7-95 STEPx_ADC_REF_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6STEPx_GAIN_BIN[1:0]R/W00bGain selection
Selects the digital (binary) gain for this sequence step.
  • 00b = Gain 1
  • 01b = Gain 2
  • 10b = Gain 4
  • 11b = Gain 8
5STEPx_CODINGR/W0bConversion data coding selection
Selects the coding of the conversion data.
  • 0b = Bipolar, two's complement format
  • 1b = Unipolar, straight binary format
4STEPx_REF_SELR/W0bReference voltage source selection
  • 0b = External voltage reference (REFP, REFN)
  • 1b = Internal voltage reference
3:0STEPx_NUM_CONV[3:0]R/W0000bNumber of ADC conversions for this sequence step
Up to 512 ADC conversions can be generated for each sequence step. This number can be programmed individually per step.
  • 0000b = 1 conversion
  • 0001b = 2 conversions
  • 0010b = 3 conversions
  • 0011b = 4 conversions
  • 0100b = 6 conversions
  • 0101b = 8 conversions
  • 0110b = 10 conversions
  • 0111b = 12 conversions
  • 1000b = 14 conversions
  • 1001b = 16 conversions
  • 1010b = 24 conversions
  • 1011b = 32 conversions
  • 1100b = 64 conversions
  • 1101b = 128 conversions
  • 1110b = 256 conversions
  • 1111b = 512 conversions

7.6.2.3 STEPx_FLTR1_CFG Register (Address = 03h) [Reset = 01h]

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Figure 7-115 STEPx_FLTR1_CFG Register
76543210
RESERVEDSTEPx_FLTR_MODESTEPx_FLTR_OSR[4:0]
R-00bR/W-0bR/W-00001b
Table 7-96 STEPx_FLTR1_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR00bReserved
Always reads 00b
5STEPx_FLTR_MODER/W0bDigital filter mode selection
Select sinc3 or sinc4 first stage filter.
  • 0b = sinc4 first stage filter
  • 1b = sinc3 first stage filter
4:0STEPx_FLTR_OSR[4:0]R/W00001bDigital filter oversampling selection
These bits select the combination of oversampling ratio and sinc filter operation. Sincx = sinc3 or sinc4 filter selection made by STEPx_FLTR_MODE bit. The output data rate is equal to fCLK/2/OSR.
  • 00000b = SINCx, OSR = 12
  • 00001b = SINCx, OSR = 16
  • 00010b = SINCx, OSR = 24
  • 00011b = SINCx, OSR = 32
  • 00100b = SINCx, OSR = 64
  • 00101b = SINCx, OSR = 128
  • 00110b = SINCx, OSR = 256
  • 00111b = SINCx, OSR = 512
  • 01000b = SINCx, OSR = 1024
  • 01001b = SINCx, OSR = 2048
  • 01010b = SINCx, OSR = 4000
  • 01011b = SINCx, OSR = 8000
  • 01100b = SINCx, OSR = 16000
  • 01101b = SINCx, OSR = 26667
  • 01110b = SINCx, OSR = 32000
  • 01111b = SINCx, OSR = 96000
  • 10000b = SINCx, OSR = 160000
  • 10001b = SINC4, OSR = 32 + SINC1, OSR = 2
  • 10010b = SINC4, OSR = 32 + SINC1, OSR = 4
  • 10011b = SINC4, OSR = 32 + SINC1, OSR = 8
  • 10100b = SINC4, OSR = 32 + SINC1, OSR = 16
  • 10101b = SINC4, OSR = 32 + SINC1, OSR = 32
  • 10110b = SINC4, OSR = 32 + SINC1, OSR = 64
  • 10111b = SINC4, OSR = 32 + SINC1, OSR = 125
  • 11000b = SINC4, OSR = 32 + SINC1, OSR = 250
  • 11001b = SINC4, OSR = 32 + SINC1, OSR = 500
  • 11010b = SINC4, OSR = 32 + SINC1, OSR = 833
  • 11011b = SINC4, OSR = 32 + SINC1, OSR =1000
  • 11100b = SINC4, OSR = 32 + SINC1, OSR =3000
  • 11101b = SINC4, OSR = 32 + SINC1, OSR = 5000
  • 11110b = SINC4, OSR = 32 + SINC1, OSR = 20 + 99 tap FIR, 25 SPS
  • 11111b = SINC4, OSR = 32 + SINC1, OSR = 20 + 124 tap FIR, 20 SPS

7.6.2.4 STEPx_DELAY_MSB_CFG Register (Address = 04h) [Reset = 00h]

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Figure 7-116 STEPx_DELAY_MSB_CFG Register
76543210
STEPx_DELAY_MSB[7:0]
R/W-00000000b
Table 7-97 STEPx_DELAY_MSB_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_DELAY_MSB[7:0]R/W00000000bConversion-start delay time selection, MSB
Programmable delay time before the start of the first conversion when START is applied or a sequence step is started (MSB byte). Delay time is given in number of fMOD clock cycles (fMOD = fCLK / 2). In total, this is a 16 bit register.

7.6.2.5 STEPx_DELAY_LSB_CFG Register (Address = 05h) [Reset = 00h]

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Figure 7-117 STEPx_DELAY_LSB_CFG Register
76543210
STEPx_DELAY_LSB[7:0]
R/W-00000000b
Table 7-98 STEPx_DELAY_LSB_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_DELAY_LSB[7:0]R/W00000000bConversion-start delay time selection, LSB
Programmable delay time before the start of the first conversion when START is applied or a sequence step is started (LSB byte). Delay time is given in number of fMOD clock cycles (fMOD = fCLK / 2). In total, this is a 16 bit register.

7.6.2.6 STEPx_OFFSET_CAL_MSB Register (Address = 06h) [Reset = 00h]

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Figure 7-118 STEPx_OFFSET_CAL_MSB Register
76543210
STEPx_OFFSET_CAL[23:16]
R/W-00000000b
Table 7-99 STEPx_OFFSET_CAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_OFFSET_CAL[23:16]R/W00000000bOffset calibration coefficient, MSB
Sets the offset calibration coefficient.

7.6.2.7 STEPx_OFFSET_CAL_ISB Register (Address = 07h) [Reset = 00h]

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Figure 7-119 STEPx_OFFSET_CAL_ISB Register
76543210
STEPx_OFFSET_CAL[15:8]
R/W-00000000b
Table 7-100 STEPx_OFFSET_CAL_ISB Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_OFFSET_CAL[15:8]R/W00000000bOffset calibration coefficient, ISB
Sets the offset calibration coefficient.

7.6.2.8 STEPx_OFFSET_CAL_LSB Register (Address = 08h) [Reset = 00h]

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Figure 7-120 STEPx_OFFSET_CAL_LSB Register
76543210
STEPx_OFFSET_CAL[7:0]
R/W-00000000b
Table 7-101 STEPx_OFFSET_CAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_OFFSET_CAL[7:0]R/W00000000bOffset calibration coefficient, LSB
Sets the offset calibration coefficient.

7.6.2.9 STEPx_GAIN_CAL_MSB Register (Address = 09h) [Reset = 40h]

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Figure 7-121 STEPx_GAIN_CAL_MSB Register
76543210
STEPx_GAIN_CAL[15:8]
R/W-01000000b
Table 7-102 STEPx_GAIN_CAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_GAIN_CAL[15:8]R/W01000000bGain calibration coefficient, MSB
Sets the gain calibration coefficient.

7.6.2.10 STEPx_GAIN_CAL_LSB Register (Address = 0Ah) [Reset = 00h]

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Figure 7-122 STEPx_GAIN_CAL_LSB Register
76543210
STEPx_GAIN_CAL[7:0]
R/W-00000000b
Table 7-103 STEPx_GAIN_CAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_GAIN_CAL[7:0]R/W00000000bGain calibration coefficient, LSB
Sets the gain calibration coefficient.

7.6.2.11 STEPx_OW_SYSMON_CFG Register (Address = 0Bh) [Reset = 00h]

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Figure 7-123 STEPx_OW_SYSMON_CFG Register
76543210
RESERVEDSTEPx_OWCS_ENRESERVEDSTEPx_SYS_MON[3:0]
R-0bR/W-0bR-00bR/W-0000b
Table 7-104 STEPx_OW_SYSMON_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved
Always reads 0b
6STEPx_OWCS_ENR/W0bOpen Wire/Burnout current source enable
Enables the open wire detect current source.
  • 0b = disabled
  • 1b = enabled
5:4RESERVEDR00bReserved
Always reads 00b
3:0STEPx_SYS_MON[3:0]R/W0000bSystem monitor input selection
Selects the system monitor input for the ADC. The AIN[4:0] bits have no effect when one of the system monitors is selected. The analog inputs as well as the TDAC muxed signals are disconnected from the buffer when a system monitor is selected. Internal 2.5V diagnostic reference is used for all settings.
  • 0000b = off (monitors not selected)
  • 0001b = Internal short: Positive and negative inputs shorted to AVSS
  • 0010b = Temperature Sensor
  • 0011b = (AVDD-AVSS)/3
  • 0100b = (CAPA-AVSS)/1
  • 0101b = (IOVDD-DGND)/3
  • 0110b = (CAPD-DGND)/1
  • 0111b = (REFP-REFN)/3
  • 1000b = (RESP-RESN)/3
  • 1001b = off (monitors not selected)
  • 1010b = off (monitors not selected)
  • 1011b = off (monitors not selected)
  • 1100b = off (monitors not selected)
  • 1101b = off (monitors not selected)
  • 1110b = off (monitors not selected)
  • 1111b = off (monitors not selected)

7.6.2.12 STEPx_TDAC_CFG0 Register (Address = 0Ch) [Reset = 00h]

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Figure 7-124 STEPx_TDAC_CFG0 Register
76543210
RESERVEDSTEPx_TDAC_VAL[4:0]
R-000bR/W-00000b
Table 7-105 STEPx_TDAC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR000bReserved
Always reads 000b
4:0STEPx_TDAC_VAL[4:0]R/W00000bTestDAC output value selection
This is a 5-bit DAC with straight binary coding (equidistant test points). Reference value is same as selected on global page but uses the diagnostic/redundant reference.

7.6.2.13 STEPx_TDAC_CFG1 Register (Address = 0Dh) [Reset = 00h]

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Figure 7-125 STEPx_TDAC_CFG1 Register
76543210
RESERVEDSTEPx_TDAC_SEL[4:0]
R-000bR/W-00000b
Table 7-106 STEPx_TDAC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR000bReserved
Always reads 000b
4:0STEPx_TDAC_SEL[4:0]R/W00000bTest DAC multiplexer input selection
This register is ignored if system monitors are active. Selects the multiplexer channel for injection of Test DAC output signal.
  • 00000b = open
  • 00001b = TDAC unbuffered to positive input; negative input is connected to AVSS
  • 00010b = TDAC unbuffered to negative input, positive input is connected to AVSS
  • 00011b = AIN0
  • 00100b = AIN1
  • 00101b = AIN2
  • 00110b = AIN3
  • 00111b = AIN4
  • 01000b = AIN5
  • 01001b = AIN6
  • 01010b = AIN7
  • 01011b = AIN8
  • 01100b = AIN9
  • 01101b = AIN10
  • 01110b = AIN11
  • 01111b = AIN12
  • 10000b = AIN13
  • 10001b = AIN14
  • 10010b = AIN15
  • 10011b = REFP/TDAC pin
  • 10100b = open
  • 10101b = open
  • 10110b = open
  • 10111b = open
  • 11000b = open
  • 11001b = open
  • 11010b = open
  • 11011b = open
  • 11100b = open
  • 11101b = open
  • 11110b = open
  • 11111b = open

7.6.2.14 STEPx_SPARE_CFG Register (Address = 0Eh) [Reset = 00h]

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Figure 7-126 STEPx_SPARE_CFG Register
76543210
STEPx_SPARE7STEPx_SPARE6STEPx_SPARE5STEPx_SPARE4STEPx_SPARE3STEPx_SPARE2STEPx_SPARE1STEPx_SPARE0
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-107 STEPx_SPARE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7STEPx_SPARE7R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
6STEPx_SPARE6R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
5STEPx_SPARE5R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
4STEPx_SPARE4R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
3STEPx_SPARE3R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
2STEPx_SPARE2R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
1STEPx_SPARE1R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
0STEPx_SPARE0R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b

7.6.2.15 STEPx_GPIO_DATA_OUT Register (Address = 10h) [Reset = 00h]

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Figure 7-127 STEPx_GPIO_DATA_OUT Register
76543210
RESERVEDSTEPx_GPIO3_DAT_OUTSTEPx_GPIO2_DAT_OUTSTEPx_GPIO1_DAT_OUTSTEPx_GPIO0_DAT_OUT
R-0000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-108 STEPx_GPIO_DATA_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0000bReserved
Always reads 0000b
3STEPx_GPIO3_DAT_OUTR/W0bGPIO3 data
Write value of GPIO3 when configured as output. Bit setting has no effect when GPIO3 is configured as input.
  • 0b = Low
  • 1b = High
2STEPx_GPIO2_DAT_OUTR/W0bGPIO2 data
Write value of GPIO2 when configured as output. Bit setting has no effect when GPIO2 is configured as input.
  • 0b = Low
  • 1b = High
1STEPx_GPIO1_DAT_OUTR/W0bGPIO1 data
Write value of GPIO1 when configured as output. Bit setting has no effect when GPIO1 is configured as input.
  • 0b = Low
  • 1b = High
0STEPx_GPIO0_DAT_OUTR/W0bGPIO0 data
Write value of GPIO0 when configured as output. Bit setting has no effect when GPIO0 is configured as input.
  • 0b = Low
  • 1b = High

7.6.2.16 STEPx_REG_MAP_CRC Register (Address = 3Dh) [Reset = 00h]

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Figure 7-128 STEPx_REG_MAP_CRC Register
76543210
STEPx_REG_MAP_CRC_VALUE[7:0]
R/W-00000000b
Table 7-109 STEPx_REG_MAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_REG_MAP_CRC_VALUE[7:0]R/W00000000bRegister map CRC for Step Configuration Page
Register map CRC value The register map CRC value is the user-computed CRC value of 0x00 to 0x10 registers in the step page. The CRC value written to this register is compared to an internal CRC calculation. If the values do not match, the REG_MAP_CRC_FAULTn bit is set. Enable the register map CRC using the REG_MAP_CRC_EN bit.

7.6.2.17 STEPx_PAGE_INDICATOR Register (Address = 3Eh) [Reset = 00h]

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Figure 7-129 STEPx_PAGE_INDICATOR Register
76543210
STEPx_PAGE_INDICATOR[7:0]
R-00000000b
Table 7-110 STEPx_PAGE_INDICATOR Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_PAGE_INDICATOR[7:0]R00000000bRegister page Indicator
Indicates the active register page.

7.6.2.18 STEPx_PAGE_POINTER Register (Address = 3Fh) [Reset = 00h]

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Figure 7-130 STEPx_PAGE_POINTER Register
76543210
STEPx_PAGE_POINTER[7:0]
R/W-00000000b
Table 7-111 STEPx_PAGE_POINTER Register Field Descriptions
BitFieldTypeResetDescription
7:0STEPx_PAGE_POINTER[7:0]R/W00000000bRegister page pointer
Selects the active register page.