Configure the behavior of the DRDY pin during sequencer operation using the DRDY_CFG[1:0] bits in the SEQUENCER_CFG register.

There are four modes available for the DRDY behavior: Depending on the mode, DRDY drives low

• every time a new conversion result is available: DRDY_CFG[1:0] = 00b
• every time a sequence step is completed: DRDY_CFG[1:0] = 01b
• every time a sequence is completed: DRDY_CFG[1:0] = 10b
• when a pre-defined threshold in the FIFO buffer is reached: DRDY_CFG[1:0] = 11b

Figure 7-22 shows the DRDY operation for driving DRDY low every time a new conversion result is available (DRDY_CFG[1:0] = 00b). Two sequence steps are shown in this example with four ADC conversions executed in the first sequence step, and three ADC conversions in the second sequence step. DRDY is driven low once every individual conversion result is available.

At the beginning of a new sequence step, the first conversion is fully settled data but incurs a delay (latency time) compared to the normal data period t_DATA = 1 / f_DATA. This latency is needed to account for full settling of the digital filter. The latency time depends on the data rate and the filter mode (see the Digital Filter section for filter latency details). The time t_SETTLE is the time from the start of the sequence step (last DRDY falling edge of the previous step) to the first DRDY falling edge within the new sequence step. The time t_SETTLE also includes the programmable delay defined by the STEPx_DELAY_MSB[7:0] bits and the STEPx_DELAY_LSB[7:0] bits in the Step Configuration Page of this sequence step. As a result, t_SETTLE is the sum of programmable delay t_{STEPx_DELAY} and filter latency t_{STEPx_FLTR_LATENCY}:

In Figure 7-22, no data are read from the ADC, thus DRDY remains low and pulses high shortly before the next DRDY falling edge. If data are read from the ADC after every conversion result completes, DRDY is forced high at the eighth SCLK edge during conversion data read operation. This is illustrated in Figure 7-23, where new data is read every time shortly after the falling edge of DRDY indicates that new data are available.

Figure 7-24 shows the DRDY operation for driving DRDY low every time a sequence step has completed (DRDY_CFG[1:0] = 01b). Two sequence steps are again shown in this example with four ADC conversions executed in the first sequence step, and three ADC conversions in the second sequence step. DRDY is driven low when the last conversion result in each sequence step is available.

Figure 7-25 shows the DRDY operation for driving DRDY low every time a full sequence completed (DRDY_CFG[1:0] = 10b). In this particular example, the complete sequence only comprises of two sequence steps (STEP0 and STEP1). DRDY is driven low when the last conversion result of the final (last) sequence step is available.

Table 7-25 summarizes the DRDY operation based on the FIFO thresholds (DRDY_CFG[1:0] = 11b). In this mode, the depth of the FIFO indicated by the FIFO_DEPTH[8:0] bits is monitored and compared against the two FIFO thresholds controlling the DRDY behavior, FIFO_THRES_A[8:0] and FIFO_THRES_B[8:0]. See the FIFO Buffer section for details on the FIFO buffer operation and the FIFO_DEPTH[8:0] bits. When the depth of the FIFO exceeds the larger of either thresholds (FIFO_THRES_A or FIFO_THRES_B), then DRDY transitions from high to low. This condition can be described as FIFO_DEPTH > FIFO_THRES_A (assuming FIFO_THRES_A is larger or equal to FIFO_THRES_B). When the depth of the FIFO is equal or smaller than the lowest of either threshold, then DRDY transitions from low to high. This condition can be described as FIFO_DEPTH < FIFO_THRES_B (assuming FIFO_THRES_B is smaller or equal to FIFO_THRES_A).

In the example shown in Figure 7-26, six samples are acquired by the ADC and then two conversion results are read from the ADC. The FIFO thresholds controlling DRDY behavior have been set to a value of five samples for the FIFO_THRES_A thresholds (FIFO_THRES_A[8:0] = 000000101b) and four samples for the FIFO_THRES_B threshold (FIFO_THRES_B[8:0] = 000000100b). In this case, FIFO_THRES_A ≥ FIFO_THRES_B. Therefore, as soon as six samples have been acquired (starting from an empty FIFO), the condition that FIFO_DEPTH > FIFO_THRES_A is met (6 > 5), and DRDY transitions from high to low. After two conversion results are read from the ADC, and no additional sample is converted in the meantime, the condition that FIFO_DEPTH ≤ FIFO_THRES_B is met (4 ≤ 4), and DRDY transitions from low to high.