SBASAE3 December   2025 ADS125H18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Divider and Input Multiplexer
      2. 7.3.2  Input Range
      3. 7.3.3  ADC Reference Voltage
      4. 7.3.4  Power Supplies
        1. 7.3.4.1 AVDD and AVSS
        2. 7.3.4.2 IOVDD
        3. 7.3.4.3 CAPA and CAPD
        4. 7.3.4.4 Power-On Reset (POR)
      5. 7.3.5  Clock Operation
        1. 7.3.5.1 Internal Oscillator
        2. 7.3.5.2 External Clock
      6. 7.3.6  Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Digital Filter Latency
        2. 7.3.7.2 Sinc3 and Sinc4 Filters
        3. 7.3.7.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.7.4 50/60Hz Notch Filters
      8. 7.3.8  FIFO Buffer
        1. 7.3.8.1 FIFO Buffer Read and Write
        2. 7.3.8.2 FIFO Overflow and Underflow
        3. 7.3.8.3 FIFO Depth Indicator
        4. 7.3.8.4 FIFO Enable and Flush
        5. 7.3.8.5 FIFO Thresholds
      9. 7.3.9  Channel Auto-Sequencer
        1. 7.3.9.1 Auto-Sequencer: Basic Operation
        2. 7.3.9.2 Sequencer Modes
          1. 7.3.9.2.1 Single-Shot Mode
          2. 7.3.9.2.2 Single Step Continuous Conversion Mode
          3. 7.3.9.2.3 Single Sequence Mode
          4. 7.3.9.2.4 Continuous Sequence Mode
        3. 7.3.9.3 Configuring the Auto-Sequencer
        4. 7.3.9.4 Starting and Stopping the Sequencer
        5. 7.3.9.5 Auto-Sequencer and DRDY Behavior
      10. 7.3.10 Offset and Gain Calibration
      11. 7.3.11 Digital PGA
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Open Wire Current Source (OWCS)
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
        5. 7.3.15.5 Resistor Divider Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125H18 Status and General Configuration Page
      2. 7.6.2 ADS125H18 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Applications
      1. 8.2.1 2-Terminal V/I PLC Analog Input Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots - Crosstalk
      2. 8.2.2 3-Terminal V/I PLC Analog Input Module
      3. 8.2.3 2 -Terminal V/I PLC Analog Input Module With Solid State Switch
      4. 8.2.4 2-Terminal, single ended V/I PLC Analog Input Module
      5. 8.2.5 2-Terminal, I-Input PLC Analog Input Module
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.13 Open Wire Current Source (OWCS)

The Open Wire Current Source (OWCS) on the ADS125H18 provides a diagnostic for a floating or “open wire” on the analog inputs. This is not a fully automated check. The user needs to perform several steps to use this feature. The basic idea is to measure resistance with the current sources with two conversions. If the input is floating, the measured resistance is higher than the predicted value. All OWCS tests are done on a single analog input. If measuring a differential signal using two AINn pins, each pin must be open-wire tested separately. The OWCS multiplexer (MUX) connects the current source to the appropriate input pin as selected by the STEPx_AIN[4:0]. Bit settings of 00000b to 01111b are valid for STEPx_AIN[4:0] when using the OWCS, all other settings - i.e. 10000b to 11111b - are ignored. Set the STEPx_OWCS_EN bit on the step configuration page x to enable the open wire current source.

The recommended sequence for performing an open wire check at an input pin AINn is:

  • Sample an ADC conversion result (baseline) without the OWCS and store the result
  • Enable the OWCS, allow time for settling
  • Collect a second ADC conversion result with the OWCS enabled
  • Calculate the delta in codes as %FSR between the two readings
  • Compare the delta against the threshold value provided in Table 7-45:
    • If delta > threshold → input can be floating
    • If delta < threshold → input is connected
Table 7-29 OWCS Decision Thresholds
DEVICE VARIANT THRESHOLD
V12 (±12V) +17.4%
V20 (±20V) +23.8%
V40 (±40V) +24.4%

The conclusion for a floating input is not definite due to the following assumption: This open-wire test assumes that the input voltage is not changing between the first and second conversion. If this assumption does not hold, a false positive can occur. Also, if the source impedance is not equal to 0 for non-fault and infinite for a fault condition, then the delta between floating and connected state is reduced, making determining if the value is sufficiently above or below the threshold difficult.

The OWCS works with either internal voltage reference value or an external reference between 2V and AVDD. Due to the ratiometric nature of the OWCS measurement, the reference value does not affect the expected delta in readings.

The OWCS decision thresholds are calculated as follows:

The OWCS current magnitude linearly tracks VREF with a nominal value of 2μA/V of VREF for the ±20V version of ADS125H18. The VREF value used by the OWCS is derived from a node after the VREF multiplexer. Thus, whatever reference, internal or external, supplies the modulator also is used by the OWCS. For a 2.5V VREF, OWCS = 2.5μA. For a 4.0V VREF, OWCS = 4.0μA. This relationship with VREF allows the threshold value mentioned previously to be a fixed % of full scale (or code value or “output referred”), that is, the value is independent of VREF. The OWCS also tracks SiCr resistance so variations in the attenuator absolute values of resistance cancels out as well.

ADS125H18 Open Wire Detection Block Diagram Figure 7-28 Open Wire Detection Block Diagram

To calculate the expected deltas, see the block diagram in Figure 7-28. Note the IR drop across the OWCS Multiplexer (OWmux) switch is not seen by the ADC and also that the input multiplexer (INmux) resistance doesn’t see the OW current. The first conversion (baseline) has the value Vconv1 = Vbaseline. The second conversion results in Vconv2 = Vbaseline + VIRdrop. The delta between the conversions is VIRdrop where the IVIRdrop = I(OWCS) × ⁢Rthev.

The OWCS tracks Vref and drops out, resulting in:

delta (%FSR) = (1μA/Ω) × (Rthev)

For non-fault (non-open) sources, assume for now Rsrc = 0. Then:

Rthev = (R1 || (R2/2))

For faulted (opened/floating) sources, assume for now Rsrc = ∞. Then:

Rthev = R2/2

Table 7-30 shows the typical deltas expected between the two ADC conversions on both a “good” or non-fault input pin, and also on a “bad” or faulted (open/floating) input.

Table 7-30 OWCS Delta in %FSR Values
DEVICE VARIANT

TYPICAL DELTA (%FSR)

Rsrc = 0

"non-fault"

TYPICAL DELTA (%FSR)

Rsrc = ∞

"fault" or "open-wire"
V12 (±12V) +16.1% +18.7%
V20 (±20V) +22.5% +25.0%
V40 (±40V) +23.7% +25.0%

To detect an open-wire condition, compare the measured delta against the threshold shown in Table 7-45. For example, if the delta is 22.9% (±20V Variant), there is no indication of an open wire.

Note that the measured delta depends on the source impedance, however Table 7-30 assumes that the source impedance is infinite for the open wire condition. In a real system, if there is a wire break with some residual connectivity, the source impedance can practically be finite, and can be in the order of several hundred kΩ or several MΩ. Figure 7-29 shows the variation of the delta with the source impedance from 10Ω to 10GΩ. Note that the delta is mostly constant from 10Ω up to about 100kΩ, then starts increasing and then approaches the ideal value closely above 10MΩ.

ADS125H18 OWCS Delta vs Source Impedance Figure 7-29 OWCS Delta vs Source Impedance

Table 7-31 lists the delta values for a few source impedance values, based on the data from Figure 7-29.

Table 7-31 OWCS Delta in %FSR Values for finite Rsource
DEVICE VARIANT

TYPICAL DELTA (%FSR)

Rsrc = 100kΩ

TYPICAL DELTA (%FSR)

Rsrc = 1MΩ

TYPICAL DELTA (%FSR)

Rsrc = 10MΩ
V12 (±12V) +16.3% +17.2% +18.4%
V20 (±20V) +22.7% +23.6% +24.7%
V40 (±40V) +23.8% +24.3% +24.9%

The thresholds suggested in Table 7-45 represent a source impedance value of 1.3MΩ (V12) and 1.4MΩ (V20, V40) according to Figure 7-29 and Table 7-31, meaning any source impedance higher than this value is considered an open wire when using the recommended thresholds. If the source impedance in the system is in the order of 100kΩ or larger, a threshold higher than listed in Table 7-45 can be chosen.

Note the settling requirement for the OWCS as follows:

The OWCS turns on and off between steps as defined on two subsequent step configuration pages. Be sure to allow time for settling before beginning a conversion. Capacitance on the sensor output reacts with the ADS125H18 resistor attenuator and slows the settling when turning on or off the OWCS. A simplified analysis below assumes the resistance is R1 and settling to 5 τ or ≅99% of the final value. Verify that there is time to settle between conversions used to calculate the delta. Keeping the source capacitance as low as possible helps to speed up settling.

Table 7-32 OWCS Settling Time
Csrc TIME TO SETTLE TO 5 τ, 99%
1pF 26μs
10pF 80μs
100pF 620μs
1nF 6ms
10nF 60ms
100nF 600ms
1µF 6s