SBASAE3 December   2025 ADS125H18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Divider and Input Multiplexer
      2. 7.3.2  Input Range
      3. 7.3.3  ADC Reference Voltage
      4. 7.3.4  Power Supplies
        1. 7.3.4.1 AVDD and AVSS
        2. 7.3.4.2 IOVDD
        3. 7.3.4.3 CAPA and CAPD
        4. 7.3.4.4 Power-On Reset (POR)
      5. 7.3.5  Clock Operation
        1. 7.3.5.1 Internal Oscillator
        2. 7.3.5.2 External Clock
      6. 7.3.6  Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Digital Filter Latency
        2. 7.3.7.2 Sinc3 and Sinc4 Filters
        3. 7.3.7.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.7.4 50/60Hz Notch Filters
      8. 7.3.8  FIFO Buffer
        1. 7.3.8.1 FIFO Buffer Read and Write
        2. 7.3.8.2 FIFO Overflow and Underflow
        3. 7.3.8.3 FIFO Depth Indicator
        4. 7.3.8.4 FIFO Enable and Flush
        5. 7.3.8.5 FIFO Thresholds
      9. 7.3.9  Channel Auto-Sequencer
        1. 7.3.9.1 Auto-Sequencer: Basic Operation
        2. 7.3.9.2 Sequencer Modes
          1. 7.3.9.2.1 Single-Shot Mode
          2. 7.3.9.2.2 Single Step Continuous Conversion Mode
          3. 7.3.9.2.3 Single Sequence Mode
          4. 7.3.9.2.4 Continuous Sequence Mode
        3. 7.3.9.3 Configuring the Auto-Sequencer
        4. 7.3.9.4 Starting and Stopping the Sequencer
        5. 7.3.9.5 Auto-Sequencer and DRDY Behavior
      10. 7.3.10 Offset and Gain Calibration
      11. 7.3.11 Digital PGA
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Open Wire Current Source (OWCS)
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
        5. 7.3.15.5 Resistor Divider Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125H18 Status and General Configuration Page
      2. 7.6.2 ADS125H18 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Applications
      1. 8.2.1 2-Terminal V/I PLC Analog Input Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots - Crosstalk
      2. 8.2.2 3-Terminal V/I PLC Analog Input Module
      3. 8.2.3 2 -Terminal V/I PLC Analog Input Module With Solid State Switch
      4. 8.2.4 2-Terminal, single ended V/I PLC Analog Input Module
      5. 8.2.5 2-Terminal, I-Input PLC Analog Input Module
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6.1 ADS125H18 Status and General Configuration Page

Table 7-54 lists the memory-mapped registers for the ADS125H18 Status and General Configuration Page registers. All register offset addresses not listed in Table 7-54 should be considered as reserved locations and the register contents should not be modified.

Table 7-54 Register Map
AddressAcronymResetBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
00hDEVICE_ID30hRESERVEDCH_CNT[1:0]DEV_ID[3:0]
01hREVISION_ID01hREV_ID[7:0]
02hSTATUS_MSB00hSTEP_INDICATOR[4:0]ADC_REF_FAULTnRESETnDRDY
03hSTATUS_LSBFFhCONV_COUNT[3:0]FIFO_FAULTnINTERNAL_FAULTnREG_WRITE_FAULTnSPI_CRC_FAULTn
04hADC_REF_STATUSB0hRESERVEDAVDD_UVnREF_UVnMOD_OVR_FAULTnRESERVED
05hDIGITAL_STATUSFFhCRC_FAULT_PAGE[5:0]MEM_INTERNAL_FAULTnREG_MAP_CRC_FAULTn
06hRESERVED00hRESERVEDRESERVED
07hGPIO_DATA_INPUT02hRESERVEDGPIO3_DAT_INGPIO2_DAT_INGPIO1_DAT_INGPIO0_DAT_IN
08hFIFO_SEQ_STATUS07hSEQ_ACTIVESEQ_COUNT[3:0]FIFO_OFnFIFO_UFnFIFO_CRC_FAULTn
09hFIFO_DEPTH_MSB00hRESERVEDFIFO_DEPTH[8]
0AhFIFO_DEPTH_LSB00hFIFO_DEPTH[7:0]
10hCONVERSION_CTRL00hSTARTSTEP_INIT[4:0]RESERVEDSTOP
11hRESET00hRESET_CODE[7:0]
12hADC_CFG0ChRESERVEDFIFO_TEST_ENRESERVEDSPEED_MODE[1:0]STBY_MODEPWDN
13hREFERENCE_CFG01hRESERVEDREF_VALREFP_BUF_EN
14hCLK_DIGITAL_CFG04hRESERVEDCLK_DIV[1:0]CLK_SELOUT_DRVSDO_MODECONT_READ_EN
15hRESERVED00hRESERVEDRESERVED
16hRESERVED00hRESERVEDRESERVED
17hGPIO_CFG0ChGPIO3_CFG[1:0]GPIO2_CFG[1:0]GPIO1_CFG[1:0]GPIO0_CFG[1:0]
18hSPARE_CFG00hSPARE7SPARE6SPARE5SPARE4SPARE3SPARE2SPARE1SPARE0
20hSEQUENCER_CFG40hSEQ_MODE[1:0]STOP_BEHAVIOR[1:0]RESERVEDDRDY_CFG[1:0]
21hSEQUENCE_STEP_EN_001hSEQ_STEP_7_ENSEQ_STEP_6_ENSEQ_STEP_5_ENSEQ_STEP_4_ENSEQ_STEP_3_ENSEQ_STEP_2_ENSEQ_STEP_1_ENSEQ_STEP_0_EN
22hSEQUENCE_STEP_EN_100hSEQ_STEP_15_ENSEQ_STEP_14_ENSEQ_STEP_13_ENSEQ_STEP_12_ENSEQ_STEP_11_ENSEQ_STEP_10_ENSEQ_STEP_9_ENSEQ_STEP_8_EN
23hSEQUENCE_STEP_EN_200hSEQ_STEP_23_ENSEQ_STEP_22_ENSEQ_STEP_21_ENSEQ_STEP_20_ENSEQ_STEP_19_ENSEQ_STEP_18_ENSEQ_STEP_17_ENSEQ_STEP_16_EN
24hSEQUENCE_STEP_EN_300hSEQ_STEP_31_ENSEQ_STEP_30_ENSEQ_STEP_29_ENSEQ_STEP_28_ENSEQ_STEP_27_ENSEQ_STEP_26_ENSEQ_STEP_25_ENSEQ_STEP_24_EN
25hFIFO_CFG00hRESERVEDFIFO_EN
26hFIFO_THRES_A_MSB00hRESERVEDFIFO_THRES_A[8]
27hFIFO_THRES_A_LSB00hFIFO_THRES_A[7:0]
28hFIFO_THRES_B_MSB00hRESERVEDFIFO_THRES_B[8]
29hFIFO_THRES_B_LSB00hFIFO_THRES_B[7:0]
2AhDIAG_MONITOR_CFG20hRESERVEDTDAC_RANGEFAULT_PIN_BEHAVIORREG_MAP_CRC_ENRESERVEDREF_UV_ENSTATUS_ENSPI_CRC_EN
2BhPOSTFILTER_CFG000hRESERVEDPF_AVG[1:0]PF_CFG
2ChPOSTFILTER_CFG100hPF7_ENPF6_ENPF5_ENPF4_ENPF3_ENPF2_ENPF1_ENPF0_EN
2DhPOSTFILTER_CFG2FFhPF7_BYPASSPF6_BYPASSPF5_BYPASSPF4_BYPASSPF3_BYPASSPF2_BYPASSPF1_BYPASSPF0_BYPASS
30hCS_FWD_CFG00hCS_FWD_EN_CODE[5:0]TIMEOUT_SEL[1:0]
31hRESERVED00hRESERVEDRESERVED
32hGPIO_FWD_CFG00hRESERVEDGPIO3_FWD_ENGPIO2_FWD_ENGPIO1__FWD_ENGPIO0_FWD_EN
3DhREG_MAP_CRC00hGENERAL_CFG_REG_MAP_CRC_VALUE[7:0]
3EhPAGE_INDICATOR00hPAGE_INDICATOR[7:0]
3FhPAGE_POINTER00hPAGE_POINTER[7:0]

Complex bit access types are encoded to fit into small table cells. Table 7-55 shows the codes that are used for access types in this section.

Table 7-55 ADS125H18 Status and General Configuration Page Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 DEVICE_ID Register (Address = 00h) [Reset = 30h]

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Figure 7-77 DEVICE_ID Register
76543210
RESERVEDCH_CNT[1:0]DEV_ID[3:0]
R-00bR-11bR-0000b
Table 7-56 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR00bReserved
Always reads 00b
5:4CH_CNT[1:0]R11bChannel count
Always reads 11b
3:0DEV_ID[3:0]R0000bDevice ID Register
Values are subject to change without notice.

7.6.1.2 REVISION_ID Register (Address = 01h) [Reset = 01h]

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Figure 7-78 REVISION_ID Register
76543210
REV_ID[7:0]
R-00000001b
Table 7-57 REVISION_ID Register Field Descriptions
BitFieldTypeResetDescription
7:0REV_ID[7:0]R00000001bRevision ID
Values are subject to change without notice.

7.6.1.3 STATUS_MSB Register (Address = 02h) [Reset = 00h]

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Figure 7-79 STATUS_MSB Register
76543210
STEP_INDICATOR[4:0]ADC_REF_FAULTnRESETnDRDY
R-00000bR-0bR/W-0bR-0b
Table 7-58 STATUS_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:3STEP_INDICATOR[4:0]R00000bSequence step indicator
Indicates the step page configuration that was used for the latest conversion result, which is currently available for readout. The step indicator resets to 00h after a device reset, in powerdown mode, or when writing to the SEQUENCER_CFG register. At the same time the conversion counter (CONV_COUNT[3:0]) resets to Fh, the sequence counter (SEQ_COUNT[3:0]) resets to 0h, and the conversion data clears.
2ADC_REF_FAULTnR0bADC or reference out of range fault flag
This bit updates when any individual bit in ADC_REF_STATUS is set. For this bit to clear, all bits in ADC_REF_STATUS must be cleared. This bit indicates either rail-to-rail buffer out of range, or modulator overrange, or reference undervoltage.
  • 0b = Out of range fault occurred
  • 1b = No out of range fault occurred
1RESETnR/W0bReset flag
Indicates a device reset occurred. Write 1b to clear bit to 1b.
  • 0b = Reset occurred
  • 1b = No reset occurred
0DRDYR0bData-ready flag
DRDY indicates when new conversion data are ready. The DRDY bit is the inverse of the DRDYn pin. Poll the bit to determine if conversion data are new or are repeated data from the last read operation.
  • 0b = Data are not new
  • 1b = Data are new

7.6.1.4 STATUS_LSB Register (Address = 03h) [Reset = FFh]

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Figure 7-80 STATUS_LSB Register
76543210
CONV_COUNT[3:0]FIFO_FAULTnINTERNAL_FAULTnREG_WRITE_FAULTnSPI_CRC_FAULTn
R-1111bR-1bR-1bR-1bR-1b
Table 7-59 STATUS_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:4CONV_COUNT[3:0]R1111bConversion counter
The conversion counter increments every time a new conversion completes. After reaching a counter value of Fh, the counter rolls over to 0h with the completion of the next conversion. The counter only resets to Fh in powerdown mode, after a device reset, or when writing to the SEQUENCER_CFG register. At the same time the sequence step indicator (STEP_INDICATOR[4:0]) resets to 00h, the sequence counter (SEQ_COUNT[3:0]) resets to 0h, and the conversion data clears. At the completion of the first conversion after reset, powerdown, or after writing to the SEQUENCER_CFG register, the counter reads 0h. When the sequencer is enabled (SEQ_MODE[1:0] = 10b or 11b), the counter always reads 0h for the first conversion of a step. When the sequencer is disabled (SEQ_MODE[1:0] = 00b or 01b), the counter value does not return to 0h if conversions with a new step page configuration complete. Reset the counter to Fh by writing to the SEQUENCER_CFG register before starting a conversion with a new step page configuration if desired.
3FIFO_FAULTnR1bFIFO fault flag
This bit updates when any individual FIFO error bit in the FIFO_SEQ_STATUS register is set. For this bit to clear, all bits in FIFO_SEQ_STATUS must be cleared.
  • 0b = FIFO fault occurred
  • 1b = No FIFO fault occurred
2INTERNAL_FAULTnR1bInternal fault flag
This bit updates when any individual bit in DIGITAL_STATUS is set. For this bit to clear, all bits in DIGITAL_STATUS must be cleared.
  • 0b = Internal fault occurred
  • 1b = No internal fault occurred
1REG_WRITE_FAULTnR1bPage or register access fault flag
Indicates a write access to an invalid register address occurred. This flag sets as soon as an invalid register address is written to, and resets at the beginning of the next SPI frame. Reading from an invalid register address does not set the flag, but can be detected from the address indication inside the SPI frame of the read command.
  • 0b = Page or register access fault occurred
  • 1b = No page or register access fault occurred
0SPI_CRC_FAULTnR1bSPI CRC fault flag
Indicates a SPI CRC fault occurred in the previous SPI frame. Bit clears automatically to 1b in every new SPI frame.
  • 0b = SPI CRC fault occurred
  • 1b = No SPI CRC fault occurred

7.6.1.5 ADC_REF_STATUS Register (Address = 04h) [Reset = B0h]

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Figure 7-81 ADC_REF_STATUS Register
76543210
RESERVEDAVDD_UVnREF_UVnMOD_OVR_FAULTnRESERVED
R-1bR/W-0bR/W-1bR/W-1bR-0000b
Table 7-60 ADC_REF_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR1bReserved
Always reads 1b.
6AVDD_UVnR/W0bAnalog supply voltage undervoltage fault flag
Indicates the AVDD supply voltage dropped below the supply undervoltage threshold. Write 1b to clear bit to 1b.
  • 0b = Supply undervoltage fault occurred
  • 1b = No supply undervoltage fault occurred
5REF_UVnR/W1bReference voltage undervoltage fault flag
Indicates the reference voltage selected by the REF_SEL[1:0] bits dropped below the reference undervoltage threshold. Write 1b to clear bit to 1b.
  • 0b = Reference undervoltage fault occurred
  • 1b = No reference undervoltage fault occurred
4MOD_OVR_FAULTnR/W1bModulator overrange fault indicator
Write 1b to clear bit to 1b.
  • 0b = Modulator overrange fault occurred
  • 1b = No modulator overrange fault occurred
3:0RESERVEDR0000bReserved
Always reads 0000b

7.6.1.6 DIGITAL_STATUS Register (Address = 05h) [Reset = FFh]

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Figure 7-82 DIGITAL_STATUS Register
76543210
CRC_FAULT_PAGE[5:0]MEM_INTERNAL_FAULTnREG_MAP_CRC_FAULTn
R-111111bR/W-1bR/W-1b
Table 7-61 DIGITAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:2CRC_FAULT_PAGE[5:0]R111111bRegister map CRC fault page indicator
Indicates which register page shows a CRC error when the REG_MAP_CRC_FAULTn indicates a CRC fault. If multiple register pages have a CRC error, then the indicator points to the first register page address where a CRC error exists. When the CRC error on the page which was indicated by the CRC_FAULT_PAGE[5:0] bit field is corrected by providing a correct register map CRC value, and another CRC error on another register page exists, the CRC_FAULT_PAGE[5:0] bit field does not update automatically. After writing 1b to the REG_MAP_CRC_FAULTn bit field, the REG_MAP_CRC_FAULTn sets to 0b again, and the CRC_FAULT_PAGE[5:0] bit field points to the next remaining first page address which has a register map CRC error. This bit field clears to 111111b when the REG_MAP_CRC_FAULTn flag is cleared to 1b.
1MEM_INTERNAL_FAULTnR/W1bInternal memory fault flag
Indicates a memory map CRC fault in the internal memory occurred or a wrong page was selected internally (PAGE_INDICATOR does not match PAGE_POINTER). Write 1b to clear bit to 1b.
  • 0b = Memory map CRC fault occurred
  • 1b = No memory map CRC fault occurred
0REG_MAP_CRC_FAULTnR/W1bRegister map CRC fault flag
Indicates a register map CRC fault in the general configuration page (register address space from 12h to 32h) or in the step configuration page occurred. Write 1b to clear bit to 1b.
  • 0b = Register map CRC fault occurred
  • 1b = No register map CRC fault occurred

7.6.1.7 GPIO_DATA_INPUT Register (Address = 07h) [Reset = 02h]

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Figure 7-83 GPIO_DATA_INPUT Register
76543210
RESERVEDGPIO3_DAT_INGPIO2_DAT_INGPIO1_DAT_INGPIO0_DAT_IN
R-0000bR-0bR-0bR-1bR-0b
Table 7-62 GPIO_DATA_INPUT Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0000bReserved
Always reads 0000b
3GPIO3_DAT_INR0bGPIO3 data
Read back value of GPIO3 when configured as digital input or output. Reads back 0b when GPIO3_CFG[1:0] = 00b.
  • 0b = Low
  • 1b = High
2GPIO2_DAT_INR0bGPIO2 data
Read back value of GPIO2 when configured as digital input or output. Reads back 0b when GPIO2_CFG[1:0] = 00b or 11b.
  • 0b = Low
  • 1b = High
1GPIO1_DAT_INR1bGPIO1 data
Read back value of GPIO1 when configured as digital input or output. Reads back 0b when GPIO1_CFG[1:0] = 00b.
  • 0b = Low
  • 1b = High
0GPIO0_DAT_INR0bGPIO0 data
Read back value of GPIO0 when configured as digital input or output. Reads back 0b when GPIO0_CFG[1:0] = 00b.
  • 0b = Low
  • 1b = High

7.6.1.8 FIFO_SEQ_STATUS Register (Address = 08h) [Reset = 07h]

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Figure 7-84 FIFO_SEQ_STATUS Register
76543210
SEQ_ACTIVESEQ_COUNT[3:0]FIFO_OFnFIFO_UFnFIFO_CRC_FAULTn
R-0bR-0000bR/W-1bR/W-1bR-1b
Table 7-63 FIFO_SEQ_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_ACTIVER0bSequencer active flag
Indicates if conversions are currently ongoing or if conversions stopped and the device is in idle, standby or powerdown mode.
  • 0b = Sequencer not active
  • 1b = Sequencer active
6:3SEQ_COUNT[3:0]R0000bCompleted sequence counter
When SEQ_MODE[1:0] = 11b, the sequence counter indicates which sequence run the latest conversion result belongs to, which is currently available for readout. The sequence counter increments with the completion of the first conversion of a new sequence run. At the completion of the first conversion of the first sequence run, the counter reads 0h. At the completion of the first conversion of the second sequence run, the counter reads 1h. After reaching a counter value of Fh, the counter rolls over to 0h with the completion of the first conversion of the next sequence run. The counter resets to 0h at the completion of the first conversion after setting the START bit to 1b or at the rising edge of the START pin. When writing to the SEQUENCER_CFG register, in powerdown mode, or after a device reset, the counter resets to 0h immediately. At the same time the sequence step indicator (STEP_INDICATOR[4:0]) resets to 00h, the conversion counter (CONV_COUNT[3:0]) resets to Fh, and the conversion data clears. The sequence counter always reads 0h when SEQ_MODE[1:0] = 00b, 01b, or 10b.
2FIFO_OFnR/W1bFIFO overflow flag
Indicates a FIFO overflow fault occurred. Write 1b to clear bit to 1b.
  • 0b = FIFO overflow occurred
  • 1b = No FIFO overflow occurred
1FIFO_UFnR/W1bFIFO underflow flag
Indicates a FIFO underflow fault occurred. Write 1b to clear bit to 1b.
  • 0b = FIFO underflow occurred
  • 1b = No FIFO underflow occurred
0FIFO_CRC_FAULTnR1bFIFO CRC fault flag
Indicates a FIFO CRC fault occurred. Write 1b to clear bit to 1b.
  • 0b = FIFO CRC fault occurred
  • 1b = No FIFO CRC fault occurred

7.6.1.9 FIFO_DEPTH_MSB Register (Address = 09h) [Reset = 00h]

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Figure 7-85 FIFO_DEPTH_MSB Register
76543210
RESERVEDFIFO_DEPTH[8]
R-0000000bR-0b
Table 7-64 FIFO_DEPTH_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0000000bReserved
Always reads 00b
0FIFO_DEPTH[8]R0bFIFO depth indicator MSB
MSB bit of the FIFO DEPTH indicator.

7.6.1.10 FIFO_DEPTH_LSB Register (Address = 0Ah) [Reset = 00h]

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Figure 7-86 FIFO_DEPTH_LSB Register
76543210
FIFO_DEPTH[7:0]
R-00000000b
Table 7-65 FIFO_DEPTH_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0FIFO_DEPTH[7:0]R00000000bFIFO depth indicator LSB
LSB bit of the FIFO DEPTH indicator.

7.6.1.11 CONVERSION_CTRL Register (Address = 10h) [Reset = 00h]

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Figure 7-87 CONVERSION_CTRL Register
76543210
STARTSTEP_INIT[4:0]RESERVEDSTOP
R/W-0bR/W-00000bR-0bR/W-0b
Table 7-66 CONVERSION_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7STARTR/W0bStart or re-start conversions of the ADC
Write 1b to start or re-start conversions of the ADC. In one-shot control mode (SEQ_MODE = 00b), one conversion is started. In start/stop control mode (SEQ_MODE=01b), conversions are started and continue until stopped by the STOP bit. Writing 1b to START while a conversion is ongoing restarts the conversion. In modes where the sequencer is enabled (SEQ_MODE=10b or 11b), the sequence is started with the step indicated by STEP_INIT[4:0]. Writing 1b to both the START and STOP bits has no effect. START is self-clearing and always reads 0b.
  • 0b = No operation
  • 1b = Start or restart conversions
6:2STEP_INIT[4:0]R/W00000bInitial execution step selector
Defines the sequence step which is executed first when a sequence is started.
1RESERVEDR0bReserved
Always reads 0b
0STOPR/W0bStop conversions of the ADC
Write 1b to stop conversions after the current conversion completes. Writing 1b to both the START and STOP has no effect. STOP is self-clearing and always reads 0b. The STOP bit clears to 0b after the ongoing sequence finished or when the START bit is set before the ongoing sequence finished, which aborts the ongoing sequence and re-starts a new sequence.
  • 0b = No operation
  • 1b = Stop conversions

7.6.1.12 RESET Register (Address = 11h) [Reset = 00h]

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Figure 7-88 RESET Register
76543210
RESET_CODE[7:0]
R/W-00000000b
Table 7-67 RESET Register Field Descriptions
BitFieldTypeResetDescription
7:0RESET_CODE[7:0]R/W00000000bDevice reset register
Write 01011010b to reset the ADC. These bits always read 00000000b.

7.6.1.13 ADC_CFG Register (Address = 12h) [Reset = 0Ch]

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Figure 7-89 ADC_CFG Register
76543210
RESERVEDFIFO_TEST_ENRESERVEDSPEED_MODE[1:0]STBY_MODEPWDN
R-0bR/W-0bR-00bR/W-11bR/W-0bR/W-0b
Table 7-68 ADC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved
Always reads 0b
6FIFO_TEST_ENR/W0bADC test mode enable (ADC counter enable)
When this test mode is enabled, the ADC data value is incremented by 1 for each data output.
  • 0b = Disabled
  • 1b = Enabled
5:4RESERVEDR00bReserved
Always reads 0000b
3:2SPEED_MODE[1:0]R/W11bPower mode selection
Selects the power mode.
  • 00b = Very-low-speed mode: 0.8MHz mod clock mode
  • 01b = Low-speed mode: 1.6MHz mod clock mode
  • 10b = Mid-speed mode: 6.4MHz mod clock mode
  • 11b = High-speed mode: 12.8MHz mod clock mode
1STBY_MODER/W0bADC standby mode selection
Selects the ADC mode when conversions stop.
  • 0b = Idle mode; ADC remains fully powered when conversions are stopped; the configuration from previous sequence step is still active.
  • 1b = Standby mode; ADC powers down when conversions are stopped. Standby mode is exited when conversions restart.
0PWDNR/W0bPowerdown mode selection
Powers down all circuitry except for the digital LDO to retain all user register settings. SPI communication is still possible. In powerdown mode, the step indicator (STEP_INDICATOR[4:0]) resets to 00h, the conversion counter (CONV_COUNT[3:0]) resets to Fh, the sequence counter (SEQ_COUNT[3:0]) resets to 0h, the conversion data clears, the FIFO clears, and the START bit and START pin are ignored. Setting the PWDN bit to 1b powers the device down immediately; any ongoing conversions are aborted. Any analog inputs configured as GPIO digital outputs transition into a Hi-Z state in powerdown mode. To maintain a certain logic level during powerdown, consider external pullup or pulldown resistors on the respective GPIO pins.
  • 0b = Active
  • 1b = Powerdown mode

7.6.1.14 REFERENCE_CFG Register (Address = 13h) [Reset = 01h]

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Figure 7-90 REFERENCE_CFG Register
76543210
RESERVEDREF_VALREFP_BUF_EN
R-000000bR/W-0bR/W-1b
Table 7-69 REFERENCE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR000000bReserved
Always reads 000000b
1REF_VALR/W0bInternal reference value selection
Selects internal reference value.
  • 0b = Internal ADC reference value is 2.5 V
  • 1b = Internal ADC reference value is 4.096 V
0REFP_BUF_ENR/W1bPositive reference buffer enable
Enables the positive reference buffer.
  • 0b = Disabled
  • 1b = Enabled

7.6.1.15 CLK_DIGITAL_CFG Register (Address = 14h) [Reset = 04h]

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Figure 7-91 CLK_DIGITAL_CFG Register
76543210
RESERVEDCLK_DIV[1:0]CLK_SELOUT_DRVSDO_MODECONT_READ_EN
R-00bR/W-00bR/W-0bR/W-1bR/W-0bR/W-0b
Table 7-70 CLK_DIGITAL_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR00bReserved
Always reads 00b
5:4CLK_DIV[1:0]R/W00bExternal clock divider ratio selection
Selects clock divider ratio.
  • 00b = Divide by 1
  • 01b = Divide by 2
  • 10b = Divide by 8
  • 11b = Divide by 16
3CLK_SELR/W0bClock selection
Selects the clock source for the device.
  • 0b = Internal oscillator
  • 1b = External clock
2OUT_DRVR/W1bDigital output drive selection
Selects the drive strength of the digital outputs.
  • 0b = Full-drive strength
  • 1b = Half-drive strength
1SDO_MODER/W0bSDO pin mode selection
This bit programs the mode of the SDO/DRDY pin.
  • 0b = Data-output only mode
  • 1b = Dual mode: data output and data ready
0CONT_READ_ENR/W0bContinuous read mode enable
Allows read of multiple bytes (conversion or register data) without CS transition.
  • 0b = Continuous read mode disabled
  • 1b = Continuous read mode enabled (daisy-chain not available)

7.6.1.16 GPIO_CFG Register (Address = 17h) [Reset = 0Ch]

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Figure 7-92 GPIO_CFG Register
76543210
GPIO3_CFG[1:0]GPIO2_CFG[1:0]GPIO1_CFG[1:0]GPIO0_CFG[1:0]
R/W-00bR/W-00bR/W-11bR/W-00b
Table 7-71 GPIO_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6GPIO3_CFG[1:0]R/W00bGPIO3 configuration
Configures the GPIO3 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Pin operates as FAULTn output (with readback)
5:4GPIO2_CFG[1:0]R/W00bGPIO2 configuration
Configures the GPIO2 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Pin operates as external clock (CLK) input. Set CLK_SEL = 1b to select the external clock for device operation.
3:2GPIO1_CFG[1:0]R/W11bGPIO1 configuration
Configures the GPIO1 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Pin operates as DRDYn output (with readback)
1:0GPIO0_CFG[1:0]R/W00bGPIO0 configuration
Configures the GPIO0 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Pin operates as START/SYNC input (with readback)

7.6.1.17 SPARE_CFG Register (Address = 18h) [Reset = 00h]

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Figure 7-93 SPARE_CFG Register
76543210
SPARE7SPARE6SPARE5SPARE4SPARE3SPARE2SPARE1SPARE0
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-72 SPARE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7SPARE7R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
6SPARE6R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
5SPARE5R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
4SPARE4R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
3SPARE3R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
2SPARE2R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
1SPARE1R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b
0SPARE0R/W0bSpare register bit
For user functions or CRC checking.
  • 0b = Spare is programmed to 0b
  • 1b = Spare is programmed to 1b

7.6.1.18 SEQUENCER_CFG Register (Address = 20h) [Reset = 40h]

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Figure 7-94 SEQUENCER_CFG Register
76543210
SEQ_MODE[1:0]STOP_BEHAVIOR[1:0]RESERVEDDRDY_CFG[1:0]
R/W-01bR/W-00bR-00bR/W-00b
Table 7-73 SEQUENCER_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6SEQ_MODE[1:0]R/W01bSequencer execution mode selection
Selects the sequencer execution mode.
  • 00b = Sequencer disabled: The sequence step defined by the STEP_INIT[4:0] pointer in the CONVERSION_CTRL register is executed only once (single-shot operation). Step enable bits are ignored in this operational mode. STEPx_NUM_CONV[3:0] bits determine the number of conversions for this sequence step.
  • 01b = Sequencer disabled: The sequence step defined by the STEP_INIT[4:0] pointer in the CONVERSION_CTRL register is executed and repeated indefinitely (continuous conversion operation). Step enable bits and STEPx_NUM_CONV[3:0] bits are ignored in this operational mode.
  • 10b = Sequencer enabled: Execute the complete sequence of steps once, starting with the step defined by the STEP_INIT[4:0] pointer. If the step defined by the STEP_INIT[4:0] pointer is not enabled, then the sequence is not executed.
  • 11b = Sequencer enabled: Execute the complete sequence of steps and repeat continuously, starting with the step defined by the STEP_INIT[4:0] pointer. If the step defined by the STEP_INIT[4:0] pointer is not enabled, then the sequence is not executed.
5:4STOP_BEHAVIOR[1:0]R/W00bSequence stop behavior selection
These bits define both the operation of the stop bit as well falling edge of START pin.
  • 00b = Stop immediately. The currrent conversion is not completed.
  • 01b = Stop after current conversion is completed.
  • 10b = Stop after current sequence step is completed. If SEQ_MODE=01b while in this mode, then stop after currrent conversion is completed.
  • 11b = Stop after full sequence is completed. If SEQ_MODE=00b while in this mode, then stop after current sequence step is completed. If SEQ_MODE=01b while in this mode, then stop after current conversion is completed.
3:2RESERVEDR00bReserved
Always reads 00b
1:0DRDY_CFG[1:0]R/W00bDRDY operational mode selection
Selects the DRDY operation mode.
  • 00b = DRDY transitions after every completed conversion.
  • 01b = DRDY transitions after every completed sequence step.
  • 10b = DRDY transitions after every completed sequence.
  • 11b = DRDY transitions are defined by two thresholds related to the FIFO buffer depth and defined in the FIFO_THRES_HI and FIFO_THRES_LO registers.

7.6.1.19 SEQUENCE_STEP_EN_0 Register (Address = 21h) [Reset = 01h]

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Figure 7-95 SEQUENCE_STEP_EN_0 Register
76543210
SEQ_STEP_7_ENSEQ_STEP_6_ENSEQ_STEP_5_ENSEQ_STEP_4_ENSEQ_STEP_3_ENSEQ_STEP_2_ENSEQ_STEP_1_ENSEQ_STEP_0_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-1b
Table 7-74 SEQUENCE_STEP_EN_0 Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_STEP_7_ENR/W0bSequencer step enable
Enables sequence step 7.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
6SEQ_STEP_6_ENR/W0bSequencer step enable
Enables sequence step 6.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
5SEQ_STEP_5_ENR/W0bSequencer step enable
Enables sequence step 5.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
4SEQ_STEP_4_ENR/W0bSequencer step enable
Enables sequence step 4.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
3SEQ_STEP_3_ENR/W0bSequencer step enable
Enables sequence step 3.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
2SEQ_STEP_2_ENR/W0bSequencer step enable
Enables sequence step 2.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
1SEQ_STEP_1_ENR/W0bSequencer step enable
Enables sequence step 1.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
0SEQ_STEP_0_ENR/W1bSequencer step enable
Enables sequence step 0.
  • 0b = Step is disabled.
  • 1b = Step is enabled.

7.6.1.20 SEQUENCE_STEP_EN_1 Register (Address = 22h) [Reset = 00h]

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Figure 7-96 SEQUENCE_STEP_EN_1 Register
76543210
SEQ_STEP_15_ENSEQ_STEP_14_ENSEQ_STEP_13_ENSEQ_STEP_12_ENSEQ_STEP_11_ENSEQ_STEP_10_ENSEQ_STEP_9_ENSEQ_STEP_8_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-75 SEQUENCE_STEP_EN_1 Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_STEP_15_ENR/W0bSequencer step enable
Enables sequence step 15.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
6SEQ_STEP_14_ENR/W0bSequencer step enable
Enables sequence step 14.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
5SEQ_STEP_13_ENR/W0bSequencer step enable
Enables sequence step 13.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
4SEQ_STEP_12_ENR/W0bSequencer step enable
Enables sequence step 12.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
3SEQ_STEP_11_ENR/W0bSequencer step enable
Enables sequence step 11.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
2SEQ_STEP_10_ENR/W0bSequencer step enable
Enables sequence step 10.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
1SEQ_STEP_9_ENR/W0bSequencer step enable
Enables sequence step 9.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
0SEQ_STEP_8_ENR/W0bSequencer step enable
Enables sequence step 8.
  • 0b = Step is disabled.
  • 1b = Step is enabled.

7.6.1.21 SEQUENCE_STEP_EN_2 Register (Address = 23h) [Reset = 00h]

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Figure 7-97 SEQUENCE_STEP_EN_2 Register
76543210
SEQ_STEP_23_ENSEQ_STEP_22_ENSEQ_STEP_21_ENSEQ_STEP_20_ENSEQ_STEP_19_ENSEQ_STEP_18_ENSEQ_STEP_17_ENSEQ_STEP_16_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-76 SEQUENCE_STEP_EN_2 Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_STEP_23_ENR/W0bSequencer step enable
Enables sequence step 23.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
6SEQ_STEP_22_ENR/W0bSequencer step enable
Enables sequence step 22.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
5SEQ_STEP_21_ENR/W0bSequencer step enable
Enables sequence step 21.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
4SEQ_STEP_20_ENR/W0bSequencer step enable
Enables sequence step 20.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
3SEQ_STEP_19_ENR/W0bSequencer step enable
Enables sequence step 19.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
2SEQ_STEP_18_ENR/W0bSequencer step enable
Enables sequence step 18.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
1SEQ_STEP_17_ENR/W0bSequencer step enable
Enables sequence step 17.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
0SEQ_STEP_16_ENR/W0bSequencer step enable
Enables sequence step 16.
  • 0b = Step is disabled.
  • 1b = Step is enabled.

7.6.1.22 SEQUENCE_STEP_EN_3 Register (Address = 24h) [Reset = 00h]

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Figure 7-98 SEQUENCE_STEP_EN_3 Register
76543210
SEQ_STEP_31_ENSEQ_STEP_30_ENSEQ_STEP_29_ENSEQ_STEP_28_ENSEQ_STEP_27_ENSEQ_STEP_26_ENSEQ_STEP_25_ENSEQ_STEP_24_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-77 SEQUENCE_STEP_EN_3 Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_STEP_31_ENR/W0bSequencer step enable
Enables sequence step 31.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
6SEQ_STEP_30_ENR/W0bSequencer step enable
Enables sequence step 30.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
5SEQ_STEP_29_ENR/W0bSequencer step enable
Enables sequence step 29.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
4SEQ_STEP_28_ENR/W0bSequencer step enable
Enables sequence step 28.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
3SEQ_STEP_27_ENR/W0bSequencer step enable
Enables sequence step 27.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
2SEQ_STEP_26_ENR/W0bSequencer step enable
Enables sequence step 26.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
1SEQ_STEP_25_ENR/W0bSequencer step enable
Enables sequence step 25.
  • 0b = Step is disabled.
  • 1b = Step is enabled.
0SEQ_STEP_24_ENR/W0bSequencer step enable
Enables sequence step 24.
  • 0b = Step is disabled.
  • 1b = Step is enabled.

7.6.1.23 FIFO_CFG Register (Address = 25h) [Reset = 00h]

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Figure 7-99 FIFO_CFG Register
76543210
RESERVEDFIFO_EN
R-0000000bR/W-0b
Table 7-78 FIFO_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0000000bReserved
Always reads 0000000b
0FIFO_ENR/W0bFIFO enable
Enables the FIFO.
  • 0b = FIFO is disabled. (FIFO is flushed and write pointer and read pointer reset, when disabled)
  • 1b = FIFO is enabled.

7.6.1.24 FIFO_THRES_A_MSB Register (Address = 26h) [Reset = 00h]

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Figure 7-100 FIFO_THRES_A_MSB Register
76543210
RESERVEDFIFO_THRES_A[8]
R-0000000bR/W-0b
Table 7-79 FIFO_THRES_A_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0000000bReserved
Always reads 0000000b
0FIFO_THRES_A[8]R/W0bDRDY FIFO threshold A configuration MSB
MSB bit of the FIFO threshold A. Upper Threshold for DRDY transition, when sequencer is in threshold mode set by DRDY_CFG=11b. Once the FIFO_DEPTH[8:0] indicator reaches the upper threshold, DRDY will transition low.

7.6.1.25 FIFO_THRES_A_LSB Register (Address = 27h) [Reset = 00h]

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Figure 7-101 FIFO_THRES_A_LSB Register
76543210
FIFO_THRES_A[7:0]
R/W-00000000b
Table 7-80 FIFO_THRES_A_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0FIFO_THRES_A[7:0]R/W00000000bDRDY FIFO threshold A configuration LSB
LSB bits of the FIFO threshold A. Upper Threshold for DRDY transition, when sequencer is in threshold mode set by DRDY_CFG=11b. Once the FIFO_DEPTH[8:0] indicator reaches the upper threshold, DRDY will transition low.

7.6.1.26 FIFO_THRES_B_MSB Register (Address = 28h) [Reset = 00h]

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Figure 7-102 FIFO_THRES_B_MSB Register
76543210
RESERVEDFIFO_THRES_B[8]
R-0000000bR/W-0b
Table 7-81 FIFO_THRES_B_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0000000bReserved
Always reads 0000000b
0FIFO_THRES_B[8]R/W0bDRDY FIFO threshold B configuration MSB
MSB bit of the FIFO threshold B. Lower Threshold for DRDY transition, when sequencer is in threshold mode set by DRDY_CFG=11b. Once the FIFO_DEPTH[8:0] indicator reaches the lower threshold, DRDY will transition high.

7.6.1.27 FIFO_THRES_B_LSB Register (Address = 29h) [Reset = 00h]

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Figure 7-103 FIFO_THRES_B_LSB Register
76543210
FIFO_THRES_B[7:0]
R/W-00000000b
Table 7-82 FIFO_THRES_B_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0FIFO_THRES_B[7:0]R/W00000000bDRDY FIFO threshold B configuration LSB
LSB bits of the FIFO threshold B. Lower Threshold for DRDY transition, when sequencer is in threshold mode set by DRDY_CFG=11b. Once the FIFO_DEPTH[8:0] indicator reaches the lower threshold, DRDY will transition high.

7.6.1.28 DIAG_MONITOR_CFG Register (Address = 2Ah) [Reset = 20h]

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Figure 7-104 DIAG_MONITOR_CFG Register
76543210
RESERVEDTDAC_RANGEFAULT_PIN_BEHAVIORREG_MAP_CRC_ENRESERVEDREF_UV_ENSTATUS_ENSPI_CRC_EN
R-0bR/W-0bR/W-1bR/W-0bR-0bR/W-0bR/W-0bR/W-0b
Table 7-83 DIAG_MONITOR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved
Always reads 0b
6TDAC_RANGER/W0bTest DAC range selection
Select test DAC range.
  • 0b = TDAC range is 2.5 V
  • 1b = TDAC range is 4.096 V
5FAULT_PIN_BEHAVIORR/W1bFault pin behavior selection
Selects fault pin behavior.
  • 0b = Fault pin output signal is static: Pin is high when no fault. Pin is low when fault occurs.
  • 1b = Fault pin output signal is dynamic: Pin is 50/50 duty cycle signal at f#MOD#/256 when no fault. Pin low when fault.
4REG_MAP_CRC_ENR/W0bRegister map CRC enable
Enables the register map CRC for the General Configuration page (register addresses 12h to 32h) as well as Step Configuration page (register addresses 0h to 10h).
  • 0b = Disabled
  • 1b = Enabled (all step configuration pages are CRC checked)
3RESERVEDR0bReserved
Always reads 0b
2REF_UV_ENR/W0bReference monitor enable
Enables the reference monitor.
  • 0b = Reference monitor disabled
  • 1b = Reference monitor enabled
1STATUS_ENR/W0bSTATUS byte output enable
Enables the STATUS byte(s) transmission on SDO as the first 2 bytes of every SPI frame.
  • 0b = Disabled
  • 1b = Enabled
0SPI_CRC_ENR/W0bSPI CRC enable
Enables the SPI CRC on SDI and SDO.
  • 0b = Disabled
  • 1b = Enabled

7.6.1.29 POSTFILTER_CFG0 Register (Address = 2Bh) [Reset = 00h]

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Figure 7-105 POSTFILTER_CFG0 Register
76543210
RESERVEDPF_AVG[1:0]PF_CFG
R-00000bR/W-00bR/W-0b
Table 7-84 POSTFILTER_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR00000bReserved
Always reads 00000b
2:1PF_AVG[1:0]R/W00bPost filter average number selection
Number of averages for the digital per-channel post filters. this field will be ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled).
  • 00b = average 4
  • 01b = average 8
  • 10b = average 16
  • 11b = average 16
0PF_CFGR/W0bPost filter cascading number selection
Cascading option for digital post filters.
  • 0b = filter not cascaded (similar to a sinc1)
  • 1b = filter cascaded 3x (similar to a sinc3)

7.6.1.30 POSTFILTER_CFG1 Register (Address = 2Ch) [Reset = 00h]

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Figure 7-106 POSTFILTER_CFG1 Register
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PF7_ENPF6_ENPF5_ENPF4_ENPF3_ENPF2_ENPF1_ENPF0_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-85 POSTFILTER_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7PF7_ENR/W0bPer channel post filter enable
Enable for post filter 7 (tied to sequencer step 7). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
6PF6_ENR/W0bPer channel post filter enable
Enable for post filter 6 (tied to sequencer step 6). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
5PF5_ENR/W0bPer channel post filter enable
Enable for post filter 5 (tied to sequencer step 5). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
4PF4_ENR/W0bPer channel post filter enable
Enable for post filter 4 (tied to sequencer step 4). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
3PF3_ENR/W0bPer channel post filter enable
Enable for post filter 3 (tied to sequencer step 3). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
2PF2_ENR/W0bPer channel post filter enable
Enable for post filter 2 (tied to sequencer step 2). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
1PF1_ENR/W0bPer channel post filter enable
Enable for post filter 1 (tied to sequencer step 1). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled
0PF0_ENR/W0bPer channel post filter enable
Enable for post filter 0 (tied to sequencer step 0). This bit is ignored if SEQ_MODE[1:0] = 00b or 01b (sequencer disabled). If postfilter is enabled, then the number of conversions per sequencer step is forced to 1, i.e. STEPx_NUM_CONV[3:0]=0. Only step 0 to step 7 are valid to be used if any post-filter is active. All other steps will be ignored.
  • 0b = disabled
  • 1b = enabled

7.6.1.31 POSTFILTER_CFG2 Register (Address = 2Dh) [Reset = FFh]

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Figure 7-107 POSTFILTER_CFG2 Register
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PF7_BYPASSPF6_BYPASSPF5_BYPASSPF4_BYPASSPF3_BYPASSPF2_BYPASSPF1_BYPASSPF0_BYPASS
R/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1b
Table 7-86 POSTFILTER_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7PF7_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 7 (tied to sequencer step 7). 0b = post filtered data is provided to the output 1b = post filter is bypassed, data is provided directly from sync4 filter
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
6PF6_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 6 (tied to sequencer step 6) In bypass mode, the data is provided directly from sync4 filter to the output.
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
5PF5_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 5 (tied to sequencer step5 ). 0b = post filtered data is provided to the output 1b = post filter is bypassed, data is provided directly from sync4 filter
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
4PF4_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 4(tied to sequencer step 4). 0b = post filtered data is provided to the output 1b = post filter is bypassed, data is provided directly from sync4 filter
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
3PF3_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 3 (tied to sequencer step 3) In bypass mode, the data is provided directly from sync4 filter to the output.
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
2PF2_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 2 (tied to sequencer step 2 ). 0b = post filtered data is provided to the output 1b = post filter is bypassed, data is provided directly from sync4 filter
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
1PF1_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 0 (tied to sequencer step 0). 0b = post filtered data is provided to the output 1b = post filter is bypassed, data is provided directly from sync4 filter
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter
0PF0_BYPASSR/W1bPer channel post filter bypass
Bypass for post filter 1 (tied to sequencer step 1). 0b = post filtered data is provided to the output 1b = post filter is bypassed, data is provided directly from sync4 filter
  • 0b = post filtered data is provided to the output
  • 1b = post filter is bypassed, data is provided directly from sync4 filter

7.6.1.32 CS_FWD_CFG Register (Address = 30h) [Reset = 00h]

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Figure 7-108 CS_FWD_CFG Register
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CS_FWD_EN_CODE[5:0]TIMEOUT_SEL[1:0]
R/W-000000bR/W-00b
Table 7-87 CS_FWD_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:2CS_FWD_EN_CODE[5:0]R/W000000bCS Forward feature enable
Write 010111b to enable the CS Forward feature. The GPIOx_FWD_EN bits select which GPIO pins operate in CS forwarding mode. These bits always read 00000000b.
1:0TIMEOUT_SEL[1:0]R/W00bTimeout enable and duration selection
Enables the SPI timeout and sets the timeout duration. When enabled the timeout checks that a rising edge of CSn happens within the selected number of MCLK cycles after a CSn falling edge. When a timeout occurs, the rest of the SPI frame on SDI is ignored before the rising edge of CSn. A new SPI transaction will start at the next CSn falling edge.
  • 00b = Timeout disable
  • 01b = Timeout enable with the short timeout, 256 MCLK cycles
  • 10b = Timeout enable with the medium length timeout, 2048 MCLK cycles
  • 11b = Timeout enable with the long timeout, 16384 MCLK cycles

7.6.1.33 GPIO_FWD_CFG Register (Address = 32h) [Reset = 00h]

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Figure 7-109 GPIO_FWD_CFG Register
76543210
RESERVEDGPIO3_FWD_ENGPIO2_FWD_ENGPIO1__FWD_ENGPIO0_FWD_EN
R-0000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-88 GPIO_FWD_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0000bReserved
Always reads 0000b
3GPIO3_FWD_ENR/W0bCS forward pin enable
GPIO3 CS forward configuration. Configures the GPIO3 pin as a CS forward / output pin. If this bit is high, the GPIO3_CFG[1:0] bits in the GPIO_CFG registers are ignored.
  • 0b = GPIO3 is not configured as CS forward.
  • 1b = GPIO3 is configured as CS forward.
2GPIO2_FWD_ENR/W0bCS forward pin enable
GPIO2 CS forward configuration. Configures the GPIO2 pin as a CS forward / output pin. If this bit is high, the GPIO2_CFG[1:0] bits in the GPIO_CFG registers are ignored.
  • 0b = GPIO2 is not configured as CS forward.
  • 1b = GPIO2 is configured as CS forward.
1GPIO1__FWD_ENR/W0bCS forward pin enable
GPIO1 CS forward configuration. Configures the GPIO1 pin as a CS forward / output pin. If this bit is high, the GPIO1_CFG[1:0] bits in the GPIO_CFG registers are ignored.
  • 0b = GPIO1 is not configured as CS forward.
  • 1b = GPIO1 is configured as CS forward.
0GPIO0_FWD_ENR/W0bCS forward pin enable
GPIO0 CS forward configuration. Configures the GPIO0 pin as a CS forward / output pin. If this bit is high, the GPIO0_CFG[1:0] bits in the GPIO_CFG registers are ignored.
  • 0b = GPIO0 is not configured as CS forward.
  • 1b = GPIO0 is configured as CS forward.

7.6.1.34 REG_MAP_CRC Register (Address = 3Dh) [Reset = 00h]

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Figure 7-110 REG_MAP_CRC Register
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GENERAL_CFG_REG_MAP_CRC_VALUE[7:0]
R/W-00000000b
Table 7-89 REG_MAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
7:0GENERAL_CFG_REG_MAP_CRC_VALUE[7:0]R/W00000000bRegister map CRC for General Configuration Page
Register map CRC value The register map CRC value is the user-computed CRC value of registers 0x12 to 0x32 in the general configuration page. The CRC value written to this register is compared to an internal CRC calculation. If the values do not match, the REG_MAP_CRC_FAULTn bit is set. Enable the register map CRC using the REG_MAP_CRC_EN bit.

7.6.1.35 PAGE_INDICATOR Register (Address = 3Eh) [Reset = 00h]

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Figure 7-111 PAGE_INDICATOR Register
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PAGE_INDICATOR[7:0]
R-00000000b
Table 7-90 PAGE_INDICATOR Register Field Descriptions
BitFieldTypeResetDescription
7:0PAGE_INDICATOR[7:0]R00000000bRegister page Indicator
Indicates the active register page.

7.6.1.36 PAGE_POINTER Register (Address = 3Fh) [Reset = 00h]

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Figure 7-112 PAGE_POINTER Register
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PAGE_POINTER[7:0]
R/W-00000000b
Table 7-91 PAGE_POINTER Register Field Descriptions
BitFieldTypeResetDescription
7:0PAGE_POINTER[7:0]R/W00000000bRegister page pointer
Selects the active register page.