SBASAE3 December   2025 ADS125H18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Divider and Input Multiplexer
      2. 7.3.2  Input Range
      3. 7.3.3  ADC Reference Voltage
      4. 7.3.4  Power Supplies
        1. 7.3.4.1 AVDD and AVSS
        2. 7.3.4.2 IOVDD
        3. 7.3.4.3 CAPA and CAPD
        4. 7.3.4.4 Power-On Reset (POR)
      5. 7.3.5  Clock Operation
        1. 7.3.5.1 Internal Oscillator
        2. 7.3.5.2 External Clock
      6. 7.3.6  Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Digital Filter Latency
        2. 7.3.7.2 Sinc3 and Sinc4 Filters
        3. 7.3.7.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.7.4 50/60Hz Notch Filters
      8. 7.3.8  FIFO Buffer
        1. 7.3.8.1 FIFO Buffer Read and Write
        2. 7.3.8.2 FIFO Overflow and Underflow
        3. 7.3.8.3 FIFO Depth Indicator
        4. 7.3.8.4 FIFO Enable and Flush
        5. 7.3.8.5 FIFO Thresholds
      9. 7.3.9  Channel Auto-Sequencer
        1. 7.3.9.1 Auto-Sequencer: Basic Operation
        2. 7.3.9.2 Sequencer Modes
          1. 7.3.9.2.1 Single-Shot Mode
          2. 7.3.9.2.2 Single Step Continuous Conversion Mode
          3. 7.3.9.2.3 Single Sequence Mode
          4. 7.3.9.2.4 Continuous Sequence Mode
        3. 7.3.9.3 Configuring the Auto-Sequencer
        4. 7.3.9.4 Starting and Stopping the Sequencer
        5. 7.3.9.5 Auto-Sequencer and DRDY Behavior
      10. 7.3.10 Offset and Gain Calibration
      11. 7.3.11 Digital PGA
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Open Wire Current Source (OWCS)
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
        5. 7.3.15.5 Resistor Divider Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125H18 Status and General Configuration Page
      2. 7.6.2 ADS125H18 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Applications
      1. 8.2.1 2-Terminal V/I PLC Analog Input Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots - Crosstalk
      2. 8.2.2 3-Terminal V/I PLC Analog Input Module
      3. 8.2.3 2 -Terminal V/I PLC Analog Input Module With Solid State Switch
      4. 8.2.4 2-Terminal, single ended V/I PLC Analog Input Module
      5. 8.2.5 2-Terminal, I-Input PLC Analog Input Module
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.16 Monitor Flags, Indicators and Counters

The ADS125H18 provides a set of monitors with according status flags to detect and indicate specific device or system faults to the host. Table 7-33 provides an overview of the available monitors. If a monitor detects a fault, the according low-active fault flag is set to 0b. Most monitors can be enabled or disabled as required using a dedicated monitor enable bit. If a monitor detects a fault, the according low-active fault flag is set to 0b. Except for the communication-related monitor fault flags, the fault flags must be cleared to 1b by the host after the fault condition is removed. The communication-related SPI CRC fault flag resets to 1b automatically in the SPI frame following a frame where no communication fault occurred.

Table 7-33 Monitor Overview
MONITOR NAME MONITOR ENABLE BIT MONITOR FAULT FLAG

FAULT FLAG REGISTER LOCATION

 FAULT FLAG RESET MECHANISM
SUPPLY, ADC AND REFERENCE MONITORS
Reset N/A RESETn STATUS_MSB Write 1b to clear bit to 1b
AVDD undervoltage N/A AVDD_UVn ADC_REF_STATUS Write 1b to clear bit to 1b
Reference undervoltage REF_UV_EN REF_UVn ADC_REF_STATUS Write 1b to clear bit to 1b
Modulator Overrange N/A MOD_OVR_FAULTn ADC_REF_STATUS Write 1b to clear bit to 1b
DIGITAL MONITORS
Register map CRC REG_MAP_CRC_EN REG_MAP_CRC_FAULTn DIGITAL_STATUS Write 1b to clear bit to 1b
Memory map CRC N/A MEM_INTERNAL_FAULTn DIGITAL_STATUS Reset or power-cycle the device
Register map CRC fault page indicator REG_MAP_CRC_EN CRC_FAULT_PAGE[5:0] DIGITAL_STATUS

Cleared to default value (111111b = no fault) when the REG_MAP_CRC_FAULTn flag is cleared
FIFO overflow flag N/A FIFO_OFn FIFO_SEQ_STATUS Write 1b to clear bit to 1b.
FIFO underflow flag N/A FIFO_UFn FIFO_SEQ_STATUS Write 1b to clear bit to 1b.
FIFO CRC fault flag N/A FIFO_CRC_FAULTn FIFO_SEQ_STATUS Write 1b to clear bit to 1b.
GPIO readback N/A N/A GPIO_DATA_INPUT N/A
COMMUNICATION MONITORS
SPI CRC N/A SPI_CRC_FAULTn STATUS_LSB Updates in every new SPI frame based on the CRC result of the previous SPI frame
Register access N/A REG_WRITE_FAULTn STATUS_LSB Updates with the next register write command

Every monitor in the ADS125H18 has a corresponding fault flag (see Table 7-33), that sets to 0b when the respective monitor detects a fault condition. As shown in Table 7-33, the RESETn and communication related fault flags are located in the STATUS_MSB or STATUS_LSB register. However the ADC, reference, FIFO and memory related fault flags are grouped together in detailed status registers as shown in Table 7-34. Instead of reading the STATUS_MSB or STATUS_LSB registers on demand using a register read command, the ADS125H18 can output a STATUS header as the first two bytes of every frame on SDO as described in the Section 7.5.3.2 section. Enable the STATUS header transmission using the STATUS_EN bit. The 16-bit STATUS header is a concatenation of the STATUS_MSB[7:0] and STATUS_LSB[7:0] register bits. To allow immediate indication of any of the ADC, reference, FIFO or memory related faults as part of the STATUS header, every detailed status register has a corresponding combined fault flag in the STATUS_MSB or STATUS_LSB register. That is, if any of the fault flags in the detailed status register set to 0b, then the combined fault flag sets to 0b as well.

Table 7-34 Detailed Status Registers and Corresponding Combined Fault Flags
DETAILED FAULT FLAGS FOR: DETAILED FAULT FLAGS DETAILED FLAG REGISTER LOCATION COMBINED FAULT FLAG IN STATUS_MSB OR STATUS_LSB REGISTER
ADC and reference AVDD_UVn ADC_REF_STATUS ADC_REF_FAULTn
REF_UVn
MOD_OVR_FAULTn
FIFO FIFO_OFn FIFO_SEQ_STATUS FIFO_FAULTn
FIFO_UFn
FIFO_CRC_FAULTn
Memory / internal errors MEM_INTERNAL_FAULTn DIGITAL_STATUS INTERNAL_FAULTn
REG_MAP_CRC_FAULTn

To clear a set combined fault flag to 1b, the host must clear all set fault flags in the corresponding detailed status register. Only after all fault flags in the detailed status register are cleared to 1b can the host clear the combined fault flag by writing 1b.

In addition to the monitors that detect faults in the device, the ADS125H18 also provides the indicators and counters shown in Table 7-35, which provide feedback about the device state or behavior.

Table 7-35 Indicator and Counter Overview
INDICATOR OR COUNTER NAME INDICATOR OR COUNTER BITS INDICATOR OR COUNTER REGISTER LOCATION
Data ready indicator DRDY FIFO_SEQ_STATUS
Sequencer active SEQ_ACTIVE FIFO_SEQ_STATUS
Sequence step indicator STEP_INDICATOR[4:0] STATUS_MSB
ADC conversion counter CONV_COUNT[3:0] STATUS_LSB
FIFO depth indicator FIFO_DEPTH[8:0] FIFO_DEPTH_MSB, FIFO_DEPTH_LSB
Completed sequence counter SEQ_COUNT[3:0] FIFO_SEQ_STATUS