SCPS299A May   2025  – September 2025 TXE8116-Q1 , TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Fail-safe Mode
      5. 7.3.5 Software Reset Call
      6. 7.3.6 Burst Mode
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Writes
      4. 7.5.4 Reads
    6. 7.6 Register Maps
      1. 7.6.1 Control Register: Read/Write and Feature Address (B23 - B16)
      2. 7.6.2 Control Register: Port Selection and Multi Port (B15 - B8)
      3. 7.6.3 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power-On Reset Requirements
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TXE8116-Q1 TXE8124-Q1 TXE8124-Q1 DGS (VSSOP) Package, 32-Pin (Top View)Figure 4-1 TXE8124-Q1 DGS (VSSOP) Package, 32-Pin (Top View)
TXE8116-Q1 TXE8124-Q1 TXE8116-Q1 DGS (VSSOP) Package, 24-Pin (Top View)Figure 4-2 TXE8116-Q1 DGS (VSSOP) Package, 24-Pin (Top View)
TXE8116-Q1 TXE8124-Q1 TXE8124-Q1 RHB (VQFN) Package, 32-Pin (Top View) Figure 4-3 TXE8124-Q1 RHB (VQFN) Package, 32-Pin (Top View)
TXE8116-Q1 TXE8124-Q1 TXE8116-Q1 RGE (VQFN) Package, 24-Pin (Top View) Figure 4-4 TXE8116-Q1 RGE (VQFN) Package, 24-Pin (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME TXE8124-Q1 VSSOP32 TXE8116-Q1 VSSOP24 TXE8124-Q1 RHB32 TXE8116-Q1 RGE24
P2.0 12 - 1 - I/O P-port input/output. At power on, Port 2 - IO #0 is configured as an input
P2.1 13 - 2 - I/O P-port input/output. At power on, Port 2 - IO #1 is configured as an input
P2.2 14 - 3 - I/O P-port input/output. At power on, Port 2 - IO #2 is configured as an input
P2.3 15 - 4 - I/O P-port input/output. At power on, Port 2 - IO #3 is configured as an input
P2.4 16 - 5 - I/O P-port input/output. At power on, Port 2 - IO #4 is configured as an input
P2.5 17 - 6 - I/O P-port input/output. At power on, Port 2 - IO #5 is configured as an input
P2.6 18 - 7 - I/O P-port input/output. At power on, Port 2 - IO #6 is configured as an input
P2.7 19 - 8 - I/O P-port input/output. At power on, Port 2 - IO #7 is configured as an input
P1.7 20 13 9 5 I/O P-port input/output. At power on, Port 1 - IO #7 is configured as an input
P1.6 21 14 10 6 I/O P-port input/output. At power on, Port 1 - IO #6 is configured as an input
P1.5 22 15 11 7 I/O P-port input/output. At power on, Port 1 - IO #5 is configured as an input
P1.4 23 16 12 8 I/O P-port input/output. At power on, Port 1 - IO #4 is configured as an input
P1.3 24 17 13 9 I/O P-port input/output. At power on, Port 1 - IO #3 is configured as an input
P1.2 25 18 14 10 I/O P-port input/output. At power on, Port 1 - IO #2 is configured as an input
P1.1 26 19 15 11 I/O P-port input/output. At power on, Port 1 - IO #1 is configured as an input
P1.0 27 20 16 12 I/O P-port input/output. At power on, Port 1 - IO #0 is configured as an input
CS 28 21 17 13 I SPI chip select input. Internal pull-up resistor
SCLK 29 22 18 14 I SPI serial clock input. Internal pull-down resistor
SDI 30 23 19 15 I SPI serial data input.
RESET/FAIL-SAFE 31 24 20 16 I Active Low reset or fail-safe input. An external pull-up resistor connects to VCC.
INT 32 1 21 17 O Open-Drain Interrupt output. An external pull-up resistor connects to VCC.
SDO 1 2 22 18 O SPI serial data output. Push-pull output
VCC 2 3 23 4 P Supply voltage
GND 3 4 24 3 G Ground
P0.0 4 5 25 19 I/O P-port input/output. At power on, Port 0 - IO #0 is configured as an input
P0.1 5 6 26 20 I/O P-port input/output. At power on, Port 0 - IO #1 is configured as an input
P0.2 6 7 27 21 I/O P-port input/output. At power on, Port 0 - IO #2 is configured as an input
P0.3 7 8 28 22 I/O P-port input/output. At power on, Port 0 - IO #3 is configured as an input
P0.4 8 9 29 23 I/O P-port input/output. At power on, Port 0 - IO #4 is configured as an input
P0.5 9 10 30 24 I/O P-port input/output. At power on, Port 0 - IO #5 is configured as an input
P0.6 10 11 31 1 I/O P-port input/output . At power on, Port 0 - IO #6 is configured as an input
P0.7 11 12 32 2 I/O P-port input/output. At power on, Port 0 - IO #7 is configured as an input
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power