SCPS299A May 2025 – September 2025 TXE8116-Q1 , TXE8124-Q1
ADVANCE INFORMATION
Communication is initiated by taking the CS pin low and clocking the SCLK pin. The first byte of the communciation are read/write configuration as well as various feature settings. The command address controls the function (input, output, polarity inversion, fail-safe etc.) while the Port address selects which ports are used. The enable/disable multi-port bit is the LSB of the second byte (B8).
Once a new command has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Upon power-up, hardware reset, or software reset, the control register defaults to 0x0.
| CONTROL REGISTER (FEATURE ADDRESS) | COMMAND BYTE (HEX) | REGISTER | MULTI PORT | PROTOCOL | POWER-UP DEFAULT |
||||
|---|---|---|---|---|---|---|---|---|---|
| B20 | B19 | B18 | B17 | B16 | |||||
| 0 | 0 | 0 | 0 | 0 | 0x0 | Scratch Register | No | Read/write byte | 0x0 |
| 0 | 0 | 0 | 0 | 1 | 0x1 |
Device_ID |
No | Read byte | 0x0 - TXE8116-Q1 0x1 - TXE8124-Q1 |
| 0 | 0 | 0 | 1 | 0 | 0x2 | Input Port Register | Yes | Read byte | 0x0 |
| 0 | 0 | 0 | 1 | 1 | 0x3 | Output Port Register | Yes | Read/write byte | 0x0 |
| 0 | 0 | 1 | 0 | 0 | 0x4 | Direction Configuration Register | Yes | Read/write byte | 0x0 |
| 0 | 0 | 1 | 0 | 1 | 0x5 | Polarity Inversion Register | Yes | Read/write byte | 0x0 |
| 0 | 0 | 1 | 1 | 0 | 0x6 | Push Pull / Open Drain Selection Register | Yes | Read/write byte | 0x0 |
| 0 | 1 | 0 | 0 | 0 | 0x8 | Pull Up or Pull Down Enable Register | Yes | Read/write byte | 0x0 |
| 0 | 1 | 0 | 0 | 1 | 0x9 | Pull Up or Pull Down Selection Register | Yes | Read/write byte | 0x0 |
| 0 | 1 | 0 | 1 | 0 | 0xA | Bus Holder Register | Yes | Read/write byte | 0x0 |
| 0 | 1 | 0 | 1 | 1 | 0xB | Smart Interrupt Register | No | Read/write byte | 0x0 |
| 0 | 1 | 1 | 0 | 0 | 0xC | Interrupt Mask Register | Yes | Read/write byte | 0xFF |
| 0 | 1 | 1 | 0 | 1 | 0xD | Input Glitch Filter Enable Register | No | Read/write byte | 0x0 |
| 0 | 1 | 1 | 1 | 0 | 0xE | Interrupt Flag Status Register | No | Read byte | 0x0 |
| 0 | 1 | 1 | 1 | 1 | 0xF | Interrupt Port Status Register | No | Read byte | 0x0 |
| 1 | 0 | 0 | 1 | 0 | 0x12 | Fail-safe Enable Register 1 | No | Read/write byte | 0x0 |
| 1 | 0 | 0 | 1 | 1 | 0x13 | Fail-safe Enable Register 2 | Yes | Read/write byte | 0x0 |
| 1 | 0 | 1 | 0 | 0 | 0x14 | Fail-safe Direction Configuration Register 1 | Yes | Read/write byte | 0x0 |
| 1 | 0 | 1 | 0 | 1 | 0x15 | Fail-safe Direction Configuration Register 2 | Yes | Read/write byte | 0x0 |
| 1 | 0 | 1 | 1 | 0 | 0x16 | Fail-safe Output Register 1 | Yes | Read/write byte | 0x0 |
| 1 | 0 | 1 | 1 | 1 | 0x17 | Fail-safe Output Register 2 | Yes | Read/write byte | 0x0 |
| 1 | 1 | 0 | 0 | 0 | 0x18 | Fail-safe Redundancy Check Register | No | Read/write byte | 0x0 |
| 1 | 1 | 0 | 0 | 1 | 0x19 | Fault Status Register | No | Read byte | 0x1 |
| 1 | 1 | 0 | 1 | 0 | 0x1A | Software Reset Register | No | Write byte | 0x0 |