SCPS299A May   2025  – September 2025 TXE8116-Q1 , TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Fail-safe Mode
      5. 7.3.5 Software Reset Call
      6. 7.3.6 Burst Mode
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Writes
      4. 7.5.4 Reads
    6. 7.6 Register Maps
      1. 7.6.1 Control Register: Read/Write and Feature Address (B23 - B16)
      2. 7.6.2 Control Register: Port Selection and Multi Port (B15 - B8)
      3. 7.6.3 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power-On Reset Requirements
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.2 SPI Data Format

The data format of the TXE81XX-Q1 is shown in Figure 7-5.

TXE8116-Q1 TXE8124-Q1 TXE81XX-Q1 SPI Word AddressFigure 7-5 TXE81XX-Q1 SPI Word Address

The length of TXE81XX-Q1 SPI word is 24 bits, shift 24 bits of data into the device in a MSB first fashion. SPI data must be stable during the rising edge of SCLK.

SDI data length must be at least 24 bits or [16 + (N*8)] bits (N is number of data byte to write; N ≥ 1). For reading data output via SDO, the data bytes start to be read back after the first 16 address bits.