This chapter gives the descriptions for each register, Register Address is the first and second byte in TXE8116-Q1/TXE8124-Q1 SPI word, and Default Value is the power up default value in the register which is the third byte in TXE8116-Q1/TXE8124-Q1 SPI word.

B23 (read/write bit) and B8 (multi port bit) are not considered in this chapter. A high (1) on B23 selects a read operation, while a low (0) on B23 selects a write operation. To enable multi port, a high (1) on B8 needs to be set.

Scratch Register (Register Address: 0x0, Default Value: 0x0)

The scratch register is a test register to read/write code from/to a blank register and resolve any coding issues.

Device ID Register (Register Address: 0x100, Default Value: 0x1)

Device ID register is a read-only register that has the device ID.

Input Port Register (Register Address: 0x200 - 0x220, Default Value: 0x0)

The input port registers reflect the incoming logic levels of the IO pins. The Input port registers are read only; writing to these registers have no effect.

Output Port Register (Register Address: 0x300 - 0x320, Default Value: 0x0)

The output port registers show the outgoing logic levels of the IO pins defined as outputs by the direction configuration register. Bit values in these registers have no effect on IO pins defined as inputs.

Direction Configuration Register (Register Address: 0x400 - 0x420, Default Value: 0x0)

The Direction Configuration registers configure the direction of the I/O pins. If a bit in these registers is set to 0, the corresponding port pin is enabled as a high-impedance input. If a bit in these registers is set to 1, the corresponding port pin is enabled as an output.

Polarity Inversion Register (Register Address: 0x500 - 0x520, Default Value: 0x0)

The polarity inversion registers allow polarity inversion of IO pins defined as inputs or outputs by the direction configuration register. If a bit in these registers is set to 1, the polarity of the corresponding port pin is inverted in the input register. If a bit in this register is set to 0, the polarity of the corresponding port is not inverted.

While in input mode, if polarity inversion is enabled, although there is an internal state toggle, no interrupt will be generated.

Push Pull / Open Drain Selection Register (Register Address: 0x600 - 0x620, Default Value: 0x0)

The push pull / open drain selection registers configure the output type. If a bit in these registers is set to 0, the corresponding port pin is enabled as a push pull output. If a bit in these registers is set to 1, the corresponding port pin is enabled as an open drain output.

Pull Up or Pull Down Enable Register (Register Address: 0x800 - 0x820, Default Value: 0x0)

The pull-up or pull-down enable registers allow the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to 1 enables the selection of pull-up/pull-down resistors. Setting the bit to 0 disconnects the pull-up/pull-down resistors from the I/O pins.

Pull Up or Pull Down Selection Register (Register Address: 0x900 - 0x920, Default Value: 0x0)

The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to 1 selects a 100kΩ pull-up resistor for that I/O pin. Setting a bit to 0 selects a 100kΩ pull-down resistor for that I/O pin. If the pull-up/down enable is 0, writing to this register will have no effect on I/O pin.

Bus Holder Register (Register Address: 0xA00 - 0xA20, Default Value: 0x0)

The bus holder registers enable or disable the input latch of the I/O pins. These registers are effective only when the IO pin is configured as an input pin. When a bit in bus holder register is 0, the state of the corresponding input IO pin is not latched.

Smart Interrupt Register (Register Address: 0xB00, Default Value: 0x0)

When the smart interrupt register bit is set to 0 (smart interrupt enabled), a state change in any input pin generates an interrupt and if the input goes back to its initial state, the interrupt is cleared.

When the smart interrupt register bit is set to 1 (smart interrupt disabled), a state change in any input pin generates an interrupt and if the input goes back to its initial state, the interrupt is not cleared. A read of the interrupt status flag register will clear the interrupt.

This feature is enabled at the port level and individual I/Os cannot be configured. As there are 3 ports in this device, bit3 to bit7 are reserved.

Interrupt Mask Register (Register Address: 0xC00 - 0xC20, Default Value: 0xFF)

Interrupt mask registers are set to 1 by default. Interrupts can be enabled by setting corresponding mask bits to 0.

If the corresponding bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted. There are 3 interrupt mask registers in this device.

Input Glitch Filter Enable Register (Register Address: 0xD00 - 0xD20, Default Value: 0x0)

Glitch filter is present at all inputs of the GPIOs. These filters are disabled by default. To enable the glitch filter, the corresponding bit of the I/O pin in the input glitch filter enable registers should be set to 1. There are 3 input glitch filter enable registers in this device.

Interrupt Flag Status Register (Register Address: 0xE00 - 0xE20, Default Value: 0x0)

A state change in any input pin generates an interrupt and this sets the corresponding interrupt flag register for the input. If the input goes back to its initial state, the interrupt flag register remains at 1 until it is read and then the interrupt is cleared.

The read-only interrupt flag status registers are used to identify the source of an interrupt. If the value is 1, it indiates that the corresponding input pin is the source of the interrupt, else it indicates that the input pin is not the source of an interrupt.

When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return 0. There are 3 interrupt flag statue registers in this device.

Interrupt Port Status Register (Register Address: 0xF00, Default Value: 0x0)

The read-only interrupt port status register is used to identify the IO port for the interrupt source. If the value is 1, it indicates that the source of the interrupt is from a pin in the given IO port. If the value is 0, it indicates that none of the input pins in the IO port is the source of an interrupt.

Fail-safe Enable Register (Register Address: 0x1200 - 0x1300, Default Value: 0x0)

The device is able to enter a fail-safe state by configuring the reset pin as a fail-safe pin. Fail-safe enable registers are used to change the functionality of the pin from reset to fail-safe. The contents of this register can get cleared during a POR event or other fault scenarios, the SPI controller has to rewrite this register every time if there is a fault scenario (which will generate an interrupt to the SPI controller, the fail-safe fault status register is to indicates the source of the interrupt).

Two fail-safe enable registers have to be written to program I/O configuration to ensure redundancy. If either of these registers get corrupted, and the contents don’t match, an interrupt will be generated. There are two fail-safe enable registers in this device.

Fail-safe Direction Configuration Register (Register Address: 0x1400 - 0x1520, Default Value: 0x0)

The fail-safe direction configuration registers configure the direction of the I/O pins when the device enters fail-safe state. If a bit in these registers is set to 0, the corresponding IO pin is enabled as a high-impedance input during fail-safe mode. If a bit in these registers is set to 1, the corresponding IO pin is enabled as an output during fail-safe mode.

Two fail-safe direction configuration registers have to be written to program I/O configuration to ensure redundancy. If either of these registers get corrupted, and the contents don’t match, an interrupt will be generated.

Fail-safe Output Register (Register Address: 0x1600 - 0x1720, Default Value: 0x0)

The fail-safe output registers show the outgoing level of the pins defined as outputs by the fail-safe direction configuration register. Bit values in these registers have no effect on IO pins defined as inputs.

Two fail-safe output registers have to be written to program I/O configuration to ensure redundancy. If either of these registers get corrupted, and the contents don’t match, an interrupt will be generated.

Fail-safe Redundancy Check Register (Register Address: 0x1800, Default Value: 0x0)

After writing all fail-safe redundant registers (fail-safe configuration + fail-safe output + device configuration for fail-safe pin if applicable), the SPI controller must enable the redundancy checks on these registers.

Fault Status Register (Register Address: 0x1900, Default Value: 0x1)

Bits in the fault status register are set during fault conditions. B0 bit is set 1 for POR recovery. B1 bit is set 1 when the fail-safe registers go out of sync. B2 bit is set when the device is in fail-safe mode. These flags are not cleared even if the fault condition goes away, but they are cleared by read operation.

Software Reset Register (Register Address: 0x1A00, Default Value: 0x0)

B0 bit in software reset register is used to trigger a device reset, B1 as 1 and B0 as 0 is used to trigger a register reset. The register is auto cleared when the reset state is entered.