SCPS299A May   2025  – September 2025 TXE8116-Q1 , TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Fail-safe Mode
      5. 7.3.5 Software Reset Call
      6. 7.3.6 Burst Mode
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Writes
      4. 7.5.4 Reads
    6. 7.6 Register Maps
      1. 7.6.1 Control Register: Read/Write and Feature Address (B23 - B16)
      2. 7.6.2 Control Register: Port Selection and Multi Port (B15 - B8)
      3. 7.6.3 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power-On Reset Requirements
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.7 Daisy Chain

Multiple TXE81XX-Q1 devices can be connected in a daisy chain configuration to expand the number of I/O ports supported. The controller first transmits the register address of the farthest device in the chain (the device furthest from the controller’s SDI and closest to the controller’s SDO). Following the header, this register address is sent first, initiating communication with the farthest device.

As the communication progresses along the chain, the register address of each subsequent device is transmitted in order. Finally, the register address of the closest device to the controller (connected to the SDI closest to the controller) is sent last. This ensures that data flows sequentially through the chain, with each device receiving and forwarding data to the next device in the sequence.

Each SPI transaction consists of 4 types of segments: Status, Header, Address (Register Address) and Data as shown below. Header is an optional segment, present only when daisy chain is enabled.

The SPI data input data on SDI is sampled on the low to high edge of SCLK. The SPI output data on SDO is changed on the high to low edge of SCLK.

Refer to Figure 7-3 for the frames of daisy chained transaction. The same sequencing is repeated throughout the entire chain until the final device is reached.

TXE8116-Q1 TXE8124-Q1 SPI Daisy Chain Data FrameFigure 7-3 SPI Daisy Chain Data Frame

Header segment

Bit 15 and 14 in Header segment are the Header ID. This is used by the device controller to detect that a header segment is being received.

Bit [15:14]: the Header ID which are 0 and 1 to indicate this is a Header segment.

Bit [13]: Reserved.

Bit [12:0]: Bit 12 to 0 in Header segment determine the number of devices in the daisy chain.

Address segment (Register Address)

Bit 15 indicates SPI mode of operation (1 = Read operation 0 = Write operation). Refer to the first and second byte in Figure 7-5 for the register address.

Status segment

Status segment is 16 bits and the following is the data format:

Bit [15:14]: Both of Bit 15 and 14 are 1 to indicate this is a Status segment.

Bit [13:8]: Bit 5 to 0 in the Fault status register, refer to Fault status register.

Bit [7:0]: Bit 7 to 0 are 0.

For example, if there is a SPI daisy chain topology for a MCU and two SPI peripheral devices, refer to Figure 7-4 for the diagram and data format between the devices:

TXE8116-Q1 TXE8124-Q1 SPI Daisy Chain DiagramFigure 7-4 SPI Daisy Chain Diagram

The register address of the farthest device (farthest from MCU's SDI/closest to MCU's SDO) is sent first by the MCU after the Header and address of the closest device (SDI closest) is sent last by the MCU.