SCPS299A May   2025  – September 2025 TXE8116-Q1 , TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Fail-safe Mode
      5. 7.3.5 Software Reset Call
      6. 7.3.6 Burst Mode
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Writes
      4. 7.5.4 Reads
    6. 7.6 Register Maps
      1. 7.6.1 Control Register: Read/Write and Feature Address (B23 - B16)
      2. 7.6.2 Control Register: Port Selection and Multi Port (B15 - B8)
      3. 7.6.3 Register Descriptions
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power-On Reset Requirements
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Software Reset Call

The software reset call is a command sent from the controller on the SPI bus that instructs the SPI target devices that support the command to be reset to the power-up default state.

TXE8116-Q1/TXE8124-Q1 devices use a 24-bit SPI frame for communication. For example, to trigger register reset via software reset command, the controller can configure the SPI frame as the following:

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Here is the sample code for this command on the controller side:

// Define the SPI register addresses

#define REGISTER_CMD_BYTE 0x1A // Register command byte of reset register

#define DATA_BITS 0x2 // Set B1 as 1 and B0 as 0 to trigger register reset

#define READ_WRITE_BIT 0 // 0 for Write operation, 1 for Read operation

// Function to send a 24-bit SPI frame to the I/O expander (MSB First)

void SPI_Send(uint32_t data) {

    // Using a hardware SPI peripheral to send the 24-bit data bit by bit (MSB first)

    for (int i = 23; i >= 0; i--) {

    SPI_Transmit((data >> i) & 0x01); // Shift out MSB first

    }

}

// Function to send software reset command to the SPI I/O expander

void SPI_Software_Reset(void) {

    uint32_t frame = 0;

    // Set the Read/Write bit (bit 23)

    frame |= (READ_WRITE_BIT << 23);

    // Set the Register Address (bits 20-16)

    frame |= (REGISTER_CMD_BYTE << 16);

    // Set the Data bits (bits 7-0)

     frame |= (DATA_BITS & 0xFF); // Ensure we only use the lower 8 bits

    // Pull CS low to select the target device

    CS_LOW();

    // Send the constructed SPI frame (MSB first)

    SPI_Send(frame);

    // Pull CS high to deselect the device after transmission

    CS_HIGH();

}