SCPS299A May   2025  – September 2025 TXE8116-Q1 , TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Fail-safe Mode
      5. 7.3.5 Software Reset Call
      6. 7.3.6 Burst Mode
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Writes
      4. 7.5.4 Reads
    6. 7.6 Register Maps
      1. 7.6.1 Control Register: Read/Write and Feature Address (B23 - B16)
      2. 7.6.2 Control Register: Port Selection and Multi Port (B15 - B8)
      3. 7.6.3 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power-On Reset Requirements
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.4 Fail-safe Mode

The SPI controller has the option to set TXE81XX-Q1 to be in a fail-safe state by programing the Fail-safe Enable Register to enable this feature and change the functionality of the pin from reset to fail-safe.

This register can get cleared during a POR event or other fault scenarios. The SPI controller has to rewrite this register every time if there is a fault scenario which will generate an interrupt to the SPI controller. After the interrupt is generated, the SPI controller can read the Fault Status Register to understand the source of the interrupt.

The bit 0 in Fail-safe Enable Register must be 1 to configure TXE81XX-Q1 to be fail-safe mode.

Two Device Configuration Registers have to be written to program I/O configuration to ensure redundancy. If either of these registers get corrupted, and the contents don’t match, an interrupt will be generated.

For example, if setting I/O pin P0.1 to be output and high under fail-safe mode, the sequence to configure fail-safe mode:

  1. Configure bit 0 in the Fail-safe Enable Register 1 (Address: 0x1200) as 1
  2. Configure bit 0 in the Fail-safe Enable Register 2 (Address: 0x1300) as 1
  3. Set bit 1 (P0.1) in port 0 of Fail-safe Direction Configuration Register 1 (Address: 0x1400) to be 1
  4. Set bit 1 (P0.1) in port 0 of Fail-safe Direction Configuration Register 2 (Address: 0x1500) to be 1
  5. Set bit 1 (P0.1) in port 0 of Fail-safe Output Register 1 (Address: 0x1600) to be 1
  6. Set bit 1 (P0.1) in port 0 of Fail-safe Output Register 2 (Address: 0x1700) to be 1
  7. Set bit 0 in Fail-safe Redundancy Check Register (Address: 0x1800) to be 1
  8. Assert RESET/FAIL-SAFE pin