SLVA704A June   2015  – October 2026 INA209 , INA219 , INA220 , INA220-Q1 , INA223 , INA226 , INA226-Q1 , INA230 , INA231 , INA3221 , INA3221-Q1 , LM8323 , LM8325-1 , LM8327 , LM8328 , LM8330 , LM8333 , LM8335 , OPT3001 , OPT3001-Q1 , OPT3002 , OPT3004 , OPT3006 , OPT3007 , P82B715 , P82B96 , PCA6107 , PCA9306 , PCA9306-Q1 , PCA9515A , PCA9515B , PCA9518 , PCA9534 , PCA9534A , PCA9535 , PCA9536 , PCA9538 , PCA9539 , PCA9543A , PCA9544A , PCA9545A , PCA9546A , PCA9548A , PCA9554 , PCA9554A , PCA9555 , PCA9557 , PCF8574 , PCF8574A , PCF8575 , PCF8575C , TCA4311A , TCA5405 , TCA6408A , TCA6416A , TCA6418E , TCA6424A , TCA6507 , TCA8418 , TCA8418E , TCA8424 , TCA9406 , TCA9509 , TCA9517 , TCA9517A , TCA9534 , TCA9534A , TCA9535 , TCA9538 , TCA9539 , TCA9539-Q1 , TCA9543A , TCA9544A , TCA9545A , TCA9546A , TCA9548A , TCA9554 , TCA9554A , TCA9555 , TCA9617A , TCA9617B , TCA9800 , TCA9801 , TCA9802 , TCA9803

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Electrical Characteristics
    1. 1.1 Open-Drain for Bidirectional Communication
      1. 1.1.1 Open-Drain Pulling Low
      2. 1.1.2 Open-Drain Releasing Bus
  5. 2I2C Interface
    1. 2.1 General I2C Operation
      1. 2.1.1 START and STOP Conditions
      2. 2.1.2 Repeated START Condition
    2. 2.2 Data Validity and Byte Format
    3. 2.3 Acknowledge (ACK) and Not Acknowledge (NACK)
  6. 3I2C Data
    1. 3.1 Writing to a Target On The I2C Bus
    2. 3.2 Reading From a Target On The I2C Bus
  7. 4Revision History

3.2 Reading From a Target On The I2C Bus

Reading from a target is very similar to writing, but with some extra steps. In order to read from a target, the controller must first instruct the target which register it wishes to read from. This is done by the controller starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. Once the target acknowledges this register address, the controller sends a START condition again, followed by the target address with the R/ W bit set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases the SDA bus, but continues supplying the clock to the target. During this part of the transaction, the controller becomes the controller-receiver, and the target becomes the target-transmitter.

The controller continues sending out the clock pulses, but releases the SDA line, so that the target can transmit data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it is ready for more data. Once the controller has received the number of bytes it is expecting, it sends a NACK, signaling to the target to halt communications and release the bus. The controller follows up with a STOP condition.

Figure 3-2 shows an example of reading a single byte from a target register.

Example I2C Read from Target Device's RegisterFigure 3-2 Example I2C Read from Target Device's Register