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Product details

Parameters

Number of I/Os 8 Features Configuration registers, Interrupt pin Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Addresses 8 Rating Catalog Frequency (Max) (kHz) 400 Operating temperature range (C) -40 to 85 open-in-new Find other I2C general-purpose I/Os (GPIOs)

Package | Pins | Size

SOIC (DW) 16 77 mm² 10.3 x 7.5 TSSOP (PW) 16 22 mm² 5 x 4.4 open-in-new Find other I2C general-purpose I/Os (GPIOs)

Features

  • Low Standby Current Consumption
  • I2C to Parallel Port Expander
  • Open-Drain Active-Low Interrupt Output
  • Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
  • 5-V Tolerant I/O Ports
  • 400-kHz Fast I2C Bus
  • Three Hardware Address Pins Allow up to Eight Devices on the I2C/SMBus
  • Input and Output Configuration Register
  • Polarity Inversion Register
  • Internal Power-On Reset
  • Power-Up With All Channels Configured as Inputs
  • No Glitch on Power Up
  • Noise Filter on SCL/SDA Inputs
  • Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
open-in-new Find other I2C general-purpose I/Os (GPIOs)

Description

The TCA9534A is a 16-pin device that provides 8 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol. The device can operate with a power supply voltage ranging from 1.65 V to 5.5 V, which allows for use with a wide range of devices. The device supports both 100-kHz (Standard-mode) and 400-kHz (Fast-mode) clock frequencies. I/O expanders such as the TCA9534A provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and other similar devices.

The features of the TCA9534A include an interrupt that is generated on the INT pin. This allows the master to know when an input port changes state. The A0, A1, and A2 hardware selectable address pins allow up to eight TCA9534A devices on the same I2C bus. The device can also be reset to its default sate by cycling the power supply and causing a power-on reset.

open-in-new Find other I2C general-purpose I/Os (GPIOs)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet TCA9534A Low Voltage 8-Bit I2C and SMBUS Low-Power I/O Expander With Interrupt Output and Configuration Registers datasheet (Rev. C) Jan. 19, 2017
Application note I2C Dynamic Addressing Apr. 25, 2019
Application note Choosing the Correct I2C Device for New Designs Sep. 07, 2016
Application note Understanding the I2C Bus Jun. 30, 2015
Application note Maximum Clock Frequency of I2C Bus Using Repeaters May 15, 2015
Application note I2C Bus Pull-Up Resistor Calculation Feb. 13, 2015
User guide I/O Expander EVM User's Guide (Rev. A) Jul. 25, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
49
Description

The IO expander evaluation module (EVM) lets you evaluate TI's portfolio of SMBus and I2C IO expander line devices. The TCA6424A and TCA9539 come installed on the board. The 24-pin TSSOP footprint also supports TCA6408A, TCA6416A, TCA9534, TCA9534ATCA9535, TCA9538, TCA9554, TCA9554A and TCA9555.

Features
  • IO expander evaluation through LEDs or broken out to headers
  • Input evaluation with on board pushbutton switches
  • Example code including necessary functions for each IO expander

Software development

FIRMWARE Download
SLVC564A.ZIP (2137 KB)

Design tools & simulation

SIMULATION MODEL Download
SCPM037.ZIP (148 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
DESIGN TOOL Download
I2C designer tool
I2C-DESIGNER — Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard with (...)
Features
  • GUI-based web application
  • Exportable designs
  • JSON file uploader
  • Bill of materials generator

Reference designs

REFERENCE DESIGNS Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
document-generic Schematic
REFERENCE DESIGNS Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic
REFERENCE DESIGNS Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic
REFERENCE DESIGNS Download
Energy Efficient and Isolated CANopen Interface Reference Design
TIDA-01406 — CAN and CANopen are legacy fieldbus protocols used in many applications in factory automation. Whenever high voltage could damage the end equipment there is need for isolation. Today’s smart factories utilize several energy efficient automation nodes. This reference design, which incorporates (...)
document-generic Schematic
REFERENCE DESIGNS Download
Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132 — This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is (...)
document-generic Schematic
REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic
REFERENCE DESIGNS Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SOIC (DW) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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  • Ongoing reliability monitoring

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