TCA9517

• Two-Channel Bidirectional Buffer
• I²C Bus and SMBus Compatible
• Operating Supply Voltage Range of 0.9 V to 5.5 V on A-side
• Operating Supply Voltage Range of 2.7 V to 5.5 V on B-side
• Voltage-Level Translation From 0.9 V - 5.5 V to 2.7 V - 5.5 V
• Footprint and Functional Replacement for PCA9515B
• Active-High Repeater-Enable Input
• Open-Drain I²C I/O
• 5.5-V Tolerant I²C and Enable Input Support Mixed-Mode Signal Operation
• Accommodates Standard Mode and Fast Mode I²C Devices and Multiple Masters
• High-Impedance I²C Pins When Powered-Off
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 5500 V Human-Body Model (A114-A)
  • 200 V Machine Model (A115-A)
  • 1000 V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The TCA9517 is a bidirectional buffer with level shifting capabilities for I²C and SMBus systems. It provides bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I²C and SMBus systems to be extended without degradation of performance, even during level shifting.

The TCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I²C bus, thus allowing two buses of up to 400-pF bus capacitance to be connected in an I²C application.

The TCA9517 has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are over-voltage tolerant to 5.5 V, even when the device is unpowered (V_CCB and/or V_CCA = 0 V).

The type of buffer design on the B-side prevents it from being used in series with devices which use static voltage offset. This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.

The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low feature (or the static offset voltage). This means that a low signal on the B-side translates to a nearly 0 V low on the A-side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A-side drives a hard low, and the input level is set at 0.3 × V_CCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A-side of two or more TCA9517 s can be connected together, allowing many topographies (See Figure 8 and Figure 9 ), with the A-side as the common bus. Also, the A-side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple TCA9517 s can be connected in series, A-side to B-side, with no buildup in offset voltage and with only time-of-flight delays to consider. The TCA9517 cannot be connected B-side to B-side, because of the buffered low voltage from the B-side. The B-side cannot be connected to a device with rise time accelerators.

VCCA is only used to provide the 0.3 × V_CCA reference to the A-side input comparators and for the power-good-detect circuit. The TCA9517 logic and all I/Os are powered by the VCCB pin.

As with the standard I²C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The TCA9517 has standard open-drain configuration of the I²C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I²C devices in addition to SMBus devices. Standard mode I²C devices only specify 3 mA in a generic I²C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.