SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data
Inrush Period - Overcurrent Protection

The inrush period is an optional mode of the device where it can be configured to allow the device to handle different inrush currents such as bulbs, motor stall currents, or capacitive loads at the initial turn on of a channel. The inrush period can be configured through the CAP_CHRG_CHx, INRUSH_DURATION_CHx, and INRUSH_LIMIT_CHx bits in the ILIM_CONFIG_CHx registers. If the inrush period is enabled, it will take effect in both the ACTIVE state and the LIMPHOME mode if a channel is enabled in either of these states.

The device offers two different ovecurrent protection settings in the inrush period which can be set through the CAP_CHRG_CHx bits:

  • No capacitive charging - immediate shutdown overcurrent protection (IOCP) only
  • Current limit regulation (ICL_REG)

The no capacitive charging setting, enables the device to have a different overcurrent protection (IOCP) value in the inrush period compared to steady state to allow for bulb current inrush or motor stall current. Additionally, in the no capacitive charging setting, I2T protection (if enabled) is active if VDS < VDS_LT_2V. The current limit regulation mode, allows for the device to charge up large capacitances such as input capacitors on downstream ECUs. Depending on the CAP_CHRG_CHx bit settings, the values of the INRUSH_LIMIT_CHx will change. The overcurrent protection for each channel is independent and can be set on an per channel basis.

No Capacitive Charging - CAP_CHRG_CHx = 00

The no capacitive charging setting, enables the device to have a different immediate shutdown overcurrent protection (IOCP) value in the inrush period compared to steady state operation to allow for different inrush events at startup such as bulb current inrush or motor stall current.

If CAP_CHRG_CHx [1:0] = 00, the immediate shutdown overcurrent protection (IOCP) value in the inrush period is set by the INRUSH_LIMIT_CHx [3:0] bits and the duration is set by the INRUSH_DURATION_CHx [2:0] bits. Once the inrush period duration timer expires the immediate shutdown overcurrent protection (IOCP) value will be set by the ILIMIT_SET_CHx [3:0] bits in steady state operation.

If CAP_CHRG_CHx [1:0] = 00, I2T protection (if enabled) and current sensing is available if VDS < VDS_LT_2V.

An example of this is shown in Figure 7-3.

TPS481HS04-Q1 No Capacitive Charging (CAP_CHRG_CHx [1:0] = 00) - Bulb Driving ExampleFigure 7-3 No Capacitive Charging (CAP_CHRG_CHx [1:0] = 00) - Bulb Driving Example

Current limit regulation capacitive charging mode - CAP_CHRG_CHx [1:0] = 10

The device offers a current limit regulation capacitive charging mode to charge up large downstream capacitive loads such as bulk input capacitors on ECUs. If CAP_CHRG_CHx [1:0] = 10, the current limit regulation mode will clamp the output current when the channel is initially enabled at a value set by the INRUSH_LIMIT_CHx [3:0]. The device will limit the current continuously until the capacitive load has finished charging, the inrush period expires, or a thermal shutdown has occurred. The range of settings which can be programmed through the INRUSH_LIMIT_CHx [3:0] and are specified in the electrical characteristic table as ICL_REG. If the VOUT voltage is greater than VBB - 2V and the inrush period timer has not expired, the device is able to slowly exit the current limit regulation without a large spike. An example of the current limit regulation capacitive charging mode and the slow exit before the inrush period timer expiration is shown in Figure 7-4.

TPS481HS04-Q1 Current Limit Regulation Capacitive Charging (CAP_CHRG_CHx [1:0] = 10) - ECU Input Bulk Capacitance Driving ExampleFigure 7-4 Current Limit Regulation Capacitive Charging (CAP_CHRG_CHx [1:0] = 10) - ECU Input Bulk Capacitance Driving Example