SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.3.2.1 Overcurrent Protection

The TPS481HS04-Q1 device offers the following functions to protect the device from different overcurrent events:

  • Capacitive load charging in inrush period
  • Immediate shutdown overcurrent protection (IOCP)
  • Programmable fuse protection (or I2T protection) in steady state
  • Thermal shutdown (TREL and TABS)
  • Short-circuit protection (ISCP_LPM_MAN or ISCP_LPM_AUTO) in LPMs

In regards to overcurrent protection, the device has two operation modes, an optional inrush period at channel startup and during steady state operation. The optional inrush period can be configured to allow the device to handle different inrush currents such as bulbs, motor stall currents, or capacitive loads at the initial turn on of a channel. The CAP_CHRG_CHx, INRUSH_DURATION_CHx, and INRUSH_LIMIT_CHx bits in the ILIM_CONFIG_CHx registers control the operation of the device in the inrush period. I2T protection is only active in the inrush period if CAP_CHRG_CHx = 00 and if VDS < VDS_LT_2V. Steady state operation takes over after the inrush period has completed. During steady state operation, overcurrent protection (IOCP) is active and I2T protection is active (if enabled).

During the inrush period all voltage sensing (VBB, VOUT) and FET temperature sensing can be used if enabled. Current sensing is only available in CAP_CHRG_CHx = 00 when VDS < VDS_LT_2V or after the inrush period has completed and the device is in steady state operation. All voltage sensing, FET temperature sensing, and current sensing is available in the steady operation.

Figure 7-2 provides an overview of the overcurrent protection in the optional inrush period and steady state operation.

For more details on the different protections available in the inrush period and in steady state, see the following sections. Overcurrent protection in the LPM is covered in the LPM section.

TPS481HS04-Q1 Overcurrent Protection Modes Overview Figure 7-2 Overcurrent Protection Modes Overview