SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

9.2.3 Application Curves

TPS481HS04-Q1 Startup Profile Figure 9-4 Startup Profile
TPS481HS04-Q1 CS Pulled From High to Low For Device Transition From SLEEP to CONFIG Mode, Read FLT_STAT_CHx First and Then FAULT_GLOBAL Registers to Clear These Registers and Deassert FLT/WAKE Pin Figure 9-5 CS Pulled From High to Low For Device Transition From SLEEP to CONFIG Mode, Read FLT_STAT_CHx First and Then FAULT_GLOBAL Registers to Clear These Registers and Deassert FLT/WAKE Pin
TPS481HS04-Q1 CHx_ON Bit Set From '0' to '1' With CAP_CHRG_CHx = 0x2 (Current limit regulation mode) With COUT = 680μF Figure 9-6 CHx_ON Bit Set From '0' to '1' With CAP_CHRG_CHx = 0x2 (Current limit regulation mode) With COUT = 680μF
TPS481HS04-Q1 CHx_ON Bit Set From '0' to '1' With CAP_CHRG_CHx = 0x3 (PWM method) With COUT = 680μF, LIN = 0.5μH, LOUT = 0.5μH Figure 9-7 CHx_ON Bit Set From '0' to '1' With CAP_CHRG_CHx = 0x3 (PWM method) With COUT = 680μF, LIN = 0.5μH, LOUT = 0.5μH
TPS481HS04-Q1 LPM to Active Mode Via Increase in Load Current Figure 9-8 LPM to Active Mode Via Increase in Load Current
TPS481HS04-Q1 LPM to LIMPHOME Mode When LHI is Pulled From Low to High Figure 9-9 LPM to LIMPHOME Mode When LHI is Pulled From Low to High
TPS481HS04-Q1 I2T Protection Behaviour in ACTIVE Mode Figure 9-10 I2T Protection Behaviour in ACTIVE Mode