SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.3.4 Fault Indication (FLT / WAKE)

The device provides enhanced fault reporting through a FLT/WAKE status pin and fault status bits through SPI.

The FLT/WAKE status pin allows the device to interrupt the system when a fault has occurred on the device. The FLT/WAKE status pin is an open drain output that asserts low when a fault occurs on the device. For faults which are read clear, the FLT/WAKE pin will go high if the fault no longer exists and the specific register to clear the fault is read. Indication on the FLT/WAKE pin can be masked for some faults through FAULT_MASK register. See the FAULT_MASK register for more details.

The device also provides fault information through SPI through a global fault register (FAULT_GLOBAL) and channel specific fault registers (FLT_STAT_CHx) to enable the system to quickly diagnose what caused the fault in the device. The device outputs the FAULT_GLOBAL [15:8] bits on the SDO header so these status bits can be continosly read for each SPI transaction.

For more details on each of the individual fault status bits see the FAULT_GLOBAL and FLT_STAT_CHx registers in the register map.

Table 7-3 highlights how the device signals different events through the FLT/WAKE pin and the fault status bits.

Table 7-3 Fault Reporting Table
EVENT / FAULTDETECTIONPROTECTIONFAULT_GLOBAL REPORTINGFLT_STAT_CHx REPORTINGFLT/WAKE INDICATION
FET - Overtemperature WarningYNCHx_FLTTHERMAL_WRN_CHxN
FET - Temperature shutdown (TSD)YYCHx_FLT and CHAN_OCP_I2T_TSDTHERMAL_WRN_CHxY
IOCP - Immediate shutdownYYCHx_FLT and CHAN_OCP_I2T_TSDILIMIT_CHxY
ICL_REG - Current limit regulationYYN/AN/AN
ICL_REG - Current limit regulation - inrush period expiryYYCHx_FLT and CHAN_OCP_I2T_TSDILIMIT_CHxY
ICL_REG - Current limit regulation - TSDYYCHx_FLT and CHAN_OCP_I2T_TSDILIMIT_CHx and THERMAL_SD_CHxY
Channel in TRETRY

(LATCH_CHx = 0)

YN/AN/AFLT_CHxY
Channel is latched-off

(LATCH_CHx = 1)

YN/AN/ALATCH_STAT_CHx and FLT_CHxY
Limp Home Entry (LHI = 1)YN/AGLOBAL_ERR_WRN and LIMPHOME_STATN/AN
Active I2T Accumulation or DecrementYN/AN/AI2T_MOD_CHxN
I2T ShutdownYYCHx_FLT and CHAN_OCP_I2T_TSDI2T_FLT_CHx and FLT_CHxY
VOUT shorted to VBBYN

CHx_FLT and OL_SHRT_VBB_OFF_FLT1

(if OL_SVBB_EN_CHx = 01)

OL_OFF_CHx

(if OL_SVBB_EN_CHx = 01)

Y, unless masked
Open loadOff StateYN

CHx_FLT and OL_SHRT_VBB_OFF_FLT

(if OL_SVBB_EN_CHx=10)

OL_OFF_CHx

(if OL_SVBB_EN_CHx=10)

Y, unless masked
On StateYNN/AN/AN
Reverse batteryYY, with external componentsN/AN/AN
VBB UV warningYNGLOBAL_ERR_WRN and VBB_UV_WRNN/AN
VBB_UVLOYYGLOBAL_ERR_WRN and VBB_UVLON/AY
VDD_UVLOYYGLOBAL_ERR_WRN and VDD_UVLON/AN
Power on Reset (POR)YYGLOBAL_ERR_WRN and PORN/AY
Loss of GNDYY, with RSDO ≥ 768ΩN/AN/AN
SPI Watchdog ErrorYN/AGLOBAL_ERR_WRN and WD_ERR (if WD_EN = 1)N/AY, unless masked
SPI Frame ErrorYN/AGLOBAL_ERR_WRN and SPI_ERRN/AY, unless masked
SPI CRC ErrorYN/AGLOBAL_ERR_WRN and SPI_ERR (if CRC_EN = 1)N/AY, unless masked