SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

8.2 EEPROM (NVM) Overview

TPS48xHSxx-Q1 provides user programmable Electrically Erasable Programmable Read-Only Memory (EEPROM) for some configuration registers and some customer defined programmable registers. This enables the user to reprogram the default values for these registers. Table shows which registers can be programmed through the EEPROM programming procedure.

Table 8-30 Register Overview
OffsetRegister NameEEPROM User Programmable
00hDEV_IDN
01hSLEEPN
02hLPMN
03hFAULT_GLOBALN
04hFAULT_MASKY
05h

BIST_RESULT_CH1

N
06hSW_STATEN
07h

DEVICE_TEST_CH1

N
08hDEV_CONFIGY
09hADC_CONFIGN
0AhADC_RESULT_VBBN
0BhADC_RESULT_BISTN
0ChFLT_STAT_CH1N
0DhPWM_CH1

Y

0EhILIM_CONFIG_CH1Y
0FhDIAG_CONFIG_CH1Y
10hADC_RESULT_CH1_IN
11hADC_RESULT_CH1_TN
12hADC_RESULT_CH1_VN
14hI2T_CONFIG_CH1Y

1Eh

I2T_TRIP_CH1

Y

1Fh

I2T_ACC_RD_CH1

N

35h

IOCP_CONFIG_CH1

Y

37h

UV_CONFIG

Y

3Dh

DEV_CONFIG_2

Y

3Fh

EEPROM_PROGRAM_CONTROL_STATUS

Y

EEPROM programming procedure

The default values for the user programmable registers can be reprogrammed through the below procedure. The following conditions need to be met in order to re-program the EEPROM correctly

  • VBB voltage ≥ 6V, referenced to device GND
  • VDD voltage > VDD_UVLO, referenced to device GND

Figure shows the procedure of how to re-program the default values.

TPS481HS04-Q1 EEPROM Re-Programming ProcedureFigure 8-1 EEPROM Re-Programming Procedure