SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.4.6 LIMPHOME Mode

The device offers a LIMPHOME mode to set the outputs to a desired safe state (high, low, keep state, or according DIx) in case of a SPI communication failure, system level failure (i.e. car crash), or MCU failure (software or hardware). The device can be placed into the LIMPHOME mode through the following ways:

  • LHI is pulled high

  • Watchdog timeout error

The state of the output(s) in LIMPHOME are determined by the CHx_LH_IN bits. Depending on the DI_OUT_DIS_FN_CHx bit setting the CHx_LH_IN settings can vary. See the below tables for more details on this. See the Output Disable (OUT_DIS) Function section for more details on the DI_OUT_DIS_FN_CHx bit and OUT_DIS function.

Table 7-6 CHx_LH_IN Bit Settings With DI_OUT_DIS_FN = 0
SETTING SETTING DESCRIPTION
00

Output state is set by the DI pin when in LIMPHOME mode

  • If DI = HI, then CHx = ON in LIMPHOME mode
  • If DI = LO, then CHx = OFF in LIMPHOME mode
01 Keeps the same output state from CHx_ON bit when entering LIMPHOME mode
10 Output will be OFF in LIMPHOME mode
11 Output will be ON in LIMPHOME mode
Table 7-7 CHx_LH_IN Bit Settings With DI_OUT_DIS_FN = 1
SETTING SETTING DESCRIPTION
00 Output will be OFF in LIMPHOME mode
01 Keeps the same output state from CHx_ON bit when entering LIMPHOME mode
10 Output will be OFF in LIMPHOME mode
11 Output will be ON in LIMPHOME mode

The register values are retained in the LIMPHOME mode. When the device enters LIMPHOME mode, the LIMPHOME_STAT bit in the FAULT_GLOBAL register is set high. In LIMPHOME mode, registers can be read but no write transactions can occur other than to clear the LIMPHOME_STAT bit in the FAULT_GLOBAL register to exit LIMPHOME mode. To clear the LIMPHOME_STAT bit, the LHI pin has to be low and a '1' has to be written to the LIMPHOME_STAT bit to clear the bit and to allow for the device to exit the LIMPHOME mode. Once the device exits LIMPHOME mode to ACTIVE mode, the device has full read/write access.