SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data
7.3.3.6.2 Detection With Channel Output Disabled

The device is able to detect an open load or a short-to-battery event when the channel output is disabled (FET is off). These will be referred to below as off state open load detection and off state short-to-battery detection. When the channel output is disabled, the device is able to distinguish between an open load event and a short-to-battery event through a defined sequence that will be discussed below. A block diagram for the off-state open load and off-state short-to-battery detection is shown in Figure 7-10.

TPS481HS04-Q1 Open Load and Short-to-Battery DetectionFigure 7-10 Open Load and Short-to-Battery Detection
Note: This figure assumes that the device ground and the load ground are at the same potential. In a real system, there may be a ground shift voltage of the order of 1V.

Off-State Short-to-Battery Detection

The device also integrates a pull-down current (ISHRT_VBB) for each channel which can be used to help distinguish between an open load and a short-to-battery fault when the channel is disabled. The pull-down resistor is enabled when EN_PULL_DOWN_CHx bit is set.

.

After some time delay based on output wire harness inductance, output capacitor and loading, SVBB_DIAG_EN_CHx bit can be enabled by MCU to enable an internal comparator which is used to detect if the VDS is above or below the VCHx(SHRT_VBB)

Off-State Open Load Detection

Once short to battery detection is complete without any fault then pull down resistor can be disabled and open load detection can be run. The device integrates a pull-up current source, OL_PU, for each channel which can be used to pull-up the output to determine if open load fault is present or not. The pull-up current source is enabled via EN_PULL_UP_CHx bit.

The strength of the internal pull-up can be programmed through the OL_PU_STR_CHx bits for each channel in the DIAG_CONFIG_CHx registers.

After some time delay based on output wire harness inductance, output capacitor and loading, OL_DIAG_EN_CHx bit can be enabled by MCU to enable an internal comparator which is used to detect if the output voltage is above or below the VCHx(SHRT_VBB).

TPS481HS04-Q1 Flow Chart For VOUT Short to VBB or FET Short and Open Load Detection With Channel DisabledFigure 7-11 Flow Chart For VOUT Short to VBB or FET Short and Open Load Detection With Channel Disabled