SLVSIF4 September   2026 TPS481HS04-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Driving Capacitive, Resistive and Inductive Loads
      2. 7.3.2 Protection Mechanisms
        1. 7.3.2.1 Overcurrent Protection
          1. 7.3.2.1.1 Inrush Period - Overcurrent Protection
          2. 7.3.2.1.2 Overcurrent Protection - Steady State Operation
          3. 7.3.2.1.3 Programmable Fuse Protection
          4. 7.3.2.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
        2. 7.3.2.2 Output Disable Function (OUT_DIS)
        3. 7.3.2.3 Thermal Shutdown
        4. 7.3.2.4 Reverse Battery
      3. 7.3.3 Diagnostic Mechanisms
        1. 7.3.3.1 Integrated ADC
        2. 7.3.3.2 Analog and Digital Current Sense Output
        3. 7.3.3.3 Output Voltage Measurement
        4. 7.3.3.4 MOSFET Temperature Measurement
        5. 7.3.3.5 VBB Voltage Measurement
        6. 7.3.3.6 VOUT Short-to-Battery and Open-Load
          1. 7.3.3.6.1 Measurement With Channel Output (FET) Enabled
          2. 7.3.3.6.2 Detection With Channel Output Disabled
        7. 7.3.3.7 VOUT Short-to-Battery or FET Short Detection For Power at All Times (PAAT) Loads
      4. 7.3.4 Fault Indication (FLT / WAKE)
      5. 7.3.5 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 SLEEP
      4. 7.4.4 Low Power Mode (LPM)
      5. 7.4.5 CONFIG or ACTIVE Mode
      6. 7.4.6 LIMPHOME Mode
    5. 7.5 TPS481HS04-Q1 Pre-production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS481HS04-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.4.4 Low Power Mode (LPM)

The device transitions from ACTIVE to low power mode (LPM) whenever LPM_ENTRY bit is set to '1'. In LPM, charge pump is enabled with Large or small FET ON based on LPM_MODE bit in LPM register and FLT/WAKE pin asserted high in this mode.

The device features two types of loadwakeup mechanism described in subsequent sections

Automatic Low Power Mode (LPM) to Active Mode (AUTO_LPM_ENTRY = '0'):

When the device is in low power mode (LPM), LPM_STATUS bit is set '1'. The device transitions from LPM to active mode automatically whenever load current (ICHx(LOAD)) exceeds load wakeup trigger threshold (ICHx(LWUx)) setting configured in LPM_EXIT_CURR_CHx. After load current exceeds load wakeup threshold, device automatically asserts FLT/WAKE pin low indicating the exit from the LPM. LPM_WAKE_CHx bit is also set to '1' in register map and LPM_STATUS bit is also reset to '0'.

AUTO LPM feature has to be disabled by resetting AUTO_LPM_ENTRY bit to '0'.

Automatic Low Power Mode (LPM) to Active Mode to LPM (AUTO LPM) for ECU polling (AUTO_LPM_ENTRY = '1'):

The TPS481HS04-Q1 has integrated AUTO LPM feature which can be enabled by AUTO_LPM_ENTRY bit in DEV_CONFIG_CHx register. AUTO LPM functionality provides flexibility for the device to automatically transition from active to a low IQ LPM while keeping power available to output at all times.

If AUTO_LPM_ENTRY bit is set to '1' and loadwakeup is detected by device (ICHx(LOAD) > ICHx(LWUx)) then device starts internal timer (tLPM_WAKE_DEGLITCH) based on LPM_WAKE_DEGLITCH timer setting in LPM register.

EVENT1: If ILOADx goes below IEXIT_LPM_AUTO within LPM_WAKE_DEGLITCH timer and ILOADx stays below IEXIT_LPM_AUTO threshold for AUTO_LPM_FILTER setting then device automatically transitions to LPM. FLT / WAKE is not asserted and remains high.

NOTE: It is recommended to set LPM_WAKE_DEGLITCH time more than loadwakeup current pulse time + AUTO_LPM_FILTER setting otherwise device will stay in active mode and not transition to LPM automatically.

EVENT2: If sensed ILOADx stays above IEXIT_LPM_AUTO within LPM_WAKE_DEGLITCH timer setting then device remains in active mode. FLT/WAKE is asserted low in order to indication WAKE to the MCU. MCU can reset LPM_ENTRY bit to '0' in order to de-assert the FLT/WAKE pin to high.

EVENT3: LPM_WAKE_DEGLITCH and AUTO_LPM_FILTER setting is only enabled when load wakeup is detected. These settings are disabled when FLT/WAKE is asserted low once.

Note:

AUTO LPM feature is only availabe when LPM_MODE bit is set to 1 (Large FET LPM).

TPS481HS04-Q1 Timing Diagram For Loadwakeup With AUTO LPM Entry For ECU Polling Figure 7-21 Timing Diagram For Loadwakeup With AUTO LPM Entry For ECU Polling