SLVSIL5A May   2025  – September 2025 UCC25661-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle-by-Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload Protection (OLP)
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
        4. 7.5.3.4 PFC On/Off
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.3.3 Burst Mode Thresholds Programming

Burst mode threshold programming is done by an external resistor divider connected between V5P and GNDP. Connect the center node of the external divider to LL pin. During the programming phase, a constant current ILLPrgm is fed to the LL pin. The resulting voltage is measured with an ADC (VLLA) at time TLLPrgm. After TPrgm, ILLPrgm is turned off and the voltage of the LL resistor divider is measured (VLLB).

UCC25661-Q1 LL pin ProgrammingFigure 7-20 LL pin Programming

The voltage on the LL pin after switch S1 is off (VLLB) is directly used to set the input power at which the system stops the LF Burst segment (PacketStop = VLLB).

Based on the measured VLLB voltage and the difference in voltage between VLLA and VLLB, determine the FBReplica voltage at which the controller enters HF Burst.

The equation to calculate VLLA - VLLB is given below.

Equation 7. VLLA-VLLB=Ru∥RI×ILLprgm
Equation 8. HFBurstEntry=PacketStop÷a

Constant a is user programmable as provided in the below table.

Equation 9. Ru∥RI=Rth

Equation 10 shows the FBReplica at which the controllers starts the LF Burst segment.

Equation 10. LFBurstEntry=PacketStop÷0.6

HFBurstexit and LFBurstexit thresholds have hysteresis from HFBurstentry and LFBurstentry respectively. The two hystereses are not user defined parameters. These two hystereses are dynamically estimated internally, based on the operating point of the converter.

Burst mode feature can be disabled by programming the (VLLA - VLLB).

Table 7-2 Burst Mode Externally Programmable Settings
(VLLA- VLLB) (V)a = (PacketStop ÷ HFBurstEntry) ratio Comment
>2.41NABurst disable
2.1850.45LF frequency range 200Hz to 400Hz
1.7540.50LF frequency range 200Hz to 400Hz
1.3910.55LF frequency range 200Hz to 400Hz
1.0870.60LF frequency range 200Hz to 400Hz
0.8330.65LF frequency range 200Hz to 400Hz
0.6170.70LF frequency range 200Hz to 400Hz
0.4410.75LF frequency range 200Hz to 400Hz
0.1760.80LF frequency range 200Hz to 400Hz

The ability to directly set the input power at which the system goes into various low power modes disables the burst mode and enables an extra degree of freedom in the system design.