SLVSIL5A May   2025  – September 2025 UCC25661-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle-by-Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload Protection (OLP)
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
        4. 7.5.3.4 PFC On/Off
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

All voltages are with respect to GND, −40°C < TJ < 125°C, VCC = 15V, currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VCCShort Below this threshold, use reduced start up current 0.6 1 1.4 V
VCCReStartJfet Below this threshold, re-enable JFET 10.2 V
VCCReStart HV start-up is re-enabled when VCC is below this level during start-up phase 12.5 13 13.5 V
VCCStartSelf Start-up when VCC is above this level  13.5 14 14.5 V
VCCStartExt Start-up when VCC is above this level 10.5 10.9 11.3 V
VCCStopSwitching Switching Stopped below this threshold 9 9.5 V
VCCUVLOr VCC under voltage lockout voltage (rising) 7.25 7.5 7.82 V
VCCUVLOf VCC under voltage lockout voltage hysteresis 6.5 6.8 7.1 V
VCCHold_r Jfet stop voltage during start-up programming phase 7.9 8.2 8.5 V
VCCHold_f Jfet start voltage during start-up programming phase 7.65 7.9 8.15 V
VCCShunt VCC internal clamp voltage 19 V
IVCCClamp VCC internal clamp current 15 mA
VCC_OV VCC OVP threshold 20.5 V
SUPPLY CURRENT
ICCSleep Current drawn from VCC rail during burst off period 800 µA
ICCRun Current drawn from VCC pin while gate is switching, excluding Gate Current Dead time = 1µs maximum dead time 8 mA
REGULATED SUPPLY
V5P Regulated supply voltage (1) No load 4.75 5 5.25 V
Regulated supply voltage 10mA load 4.75 5 5.25 V
V5PUVLO V5P under voltage lock out voltage (1) 4 V
IV5Pstart-upCurrLimit Max current that can be drawn on the pin when VCCP < VCCStartSelf (1) VCCP = 15V 6 mA
IV5PCurrLimit V5P at IV5P = 15mA VCCP = 15V 10.2 mA
HIGH VOLTAGE START-UP
IVCC_Charge_Low Reduced VCCP charge current from HV Pin VHV = 20V, VCC = 0V (UCC256612−Q1, UCC256614−Q1) 0.23 0.44 0.65 mA
IVCC_Charge_High Full VCCP charge current VHV = 20V, VCC = 4V, (UCC256612−Q1, UCC256614−Q1) 7.5 10 13.8 mA
BULK VOLTAGE SENSE
VBLKStartHys BLK voltage comparator hysteresis (1) For UCC256614−Q1 0.04 0.05 0.06 V
VBLKStartHys BLK voltage comparator hysteresis (1) For UCC256612−Q1, UCC256613−Q1 0.09 0.1 0.11 V
VBLKStop BLK voltage that forces LLC operation to stop 0.98 1 1.02 V
IBLKHys BLK hysteresis current  For UCC256614−Q1 1 µA
IBLKHys BLK hysteresis current  For UCC256612−Q1, UCC256613−Q1 5 µA
FEEDBACK PIN
RFBInternal Internal pull down resistor value  For UCC256614−Q1 85 100 115 kΩ
RFBInternal Internal pull down resistor value For UCC256612−Q1, UCC256613−Q1 42.5 50 57.5 kΩ
IFB FB internal current source For UCC256614−Q1 68 80 92 µA
IFB FB internal current source For UCC256612−Q1, UCC256613−Q1 136 160 184 µA
VFB FB pin voltage when FB pin sink current is at (IFB − 50µA) Iopto = 0.37 × IFB 3.3 3.5 3.7 V
ΔVFB FB pin voltage variation when FB pin sink current ranges from (Iopto = 0.37 × IFB to Iopto = 0.94 × IFB) 0.6 V
ΔVclamp FB pin voltage variation when FB pin sink current ranges from (Iopto =  0.94 × IFB) to (Iopto = 1.06 × IFB) (Iopto =  0.94 × IFB) to (Iopto = 1.06 × IFB) 0.3 V
IFBclamp Maximum FB internal current source when FB is clamped For UCC256614−Q1 75 87.5 100 μA
IFBclamp Maximum FB internal current source when FB is clamped For UCC256612−Q1, UCC256613−Q1 150 175 200 μA
ΔVFBclamp FB pin voltage variation when FB pin sink current ranges from (IIopto = 1.06IFB) to (IIopto = IFB + 0.94 × IFBClamp) (IIopto = 1.06IFB) to (IIopto = IFB + 0.94 × IFBClamp) 0.5 V
f−3dB Feedback chain −3dB cut off frequency (2) VFBReplica from 4.5V to 0.5V 1 MHz
VFBOLP OLP protection(1) 4.75 V
TOLPFault OLP protection time (1) 100 ms
RESONANT CURRENT SENSE
VISNS_OCP OCP threshold during steady state For TSET option >2.5V (1) 3.9 4 4.1 V
VISNS_OCP OCP threshold during steady state For TSET option <2.5V  3.4 3.5 3.6 V
VISNS_OCP_SS OCP threshold during soft start 2.9 3 3.1 V
nOCP Number of OCP cycles before OCP fault is tripped (1) 7
nOCP_SS Number of OCP cycles before OCP fault is tripped at start-up(2) 50
VIpolarityHyst ISNS Polarity comparator hysteresis 40 mV
VISNS_ZCS ZCS comparator +Ve threshold after Soft Start 150 mV
VISNS_ZCSn ZCS comparator −Ve threshold, after Soft Start −150 mV
VISNS_MINCURR_SS +Ve ISNS threshold during Soft Start 50 mV
VISNS_MINCURR_SSn −Ve ISNS threshold during Soft Start −50 mV
tleb Leading edge blanking for ZCS and OCP comparators(1) 250 nS
TZCSFault Fault detected when ZCS event persists for the indicated time(2) ZCS Event persists 10 mS
GATE DRIVER
VLOL LO output low voltage Isink = 20mA 0.12 V
VRVCC − VLOH LO output high voltage Isource = 20mA 0.3 V
VHOL − VHS HO output low voltage Isink = 20mA 0.12 V
VHB − VHOH HO output high voltage Isource = 20mA 0.35 V
VHB−HSUVLOFall High side gate driver UVLO falling threshold 6.4 7.25 8 V
VHB−HSUVLOHys High side gate driver UVLO threshold hysteresis 0.78 0.9 1.05 V
Isource_pk_HO HO peak source current (2) At VCCP = 12V −0.6 A
Isource_pk_LO LO peak source current (2) At VCCP = 12V −0.6 A
Isink_pk_HO HO peak sink current (2) At VCCP = 12V 1.2 A
Isink_pk_LO LO peak sink current (2) At VCCP = 12V 1.2 A
BOOTSTRAP
IBOOT_QUIESCENT (HB − HS) quiescent current HB − HS = 12V 60 70 µA
IBOOT_LEAK HB to GND leakage current VHB = 600V 0.045 20 µA
tChargeBoot Length of charge boot state(1) 230 265 300 µs
SOFT START
SSRamp Soft Start Ramp time(1) 25 ms
OVP/OTP
Vclamp_otp1 Clamp Voltage at 0mA(1) At 0mA current flowing through the clamp 1.35 1.5 1.65 V
Vclamp_otp2 Clamp Voltage at 1mA(1) At 1mA current flowing through the clamp 2.9 3.5 4.1 V
IOTP Current source on the BW/OTP pin 100 uA
VOVPpos Output voltage OVP − Threshold rising 3.5 V
VOTPNeg  OTP − Threshold falling 0.8 V
OTPCompHys OTP comparator hysteresis 60 90 130 mV
OVPCompHys OVP comparator hysteresis 60 100 145 mV
OTPBlankingstart-up OTP blanking time at start-up 50 ms
TOTPFault OTP Fault detection time 330 uS
TOVPFault OVP Fault detection time(2) 40 uS
TSET
ITSETPrgm TSET pin sourcing current for programming 10 uA
LL
ILLPrgm LL pin sourcing current for Burst mode transition threshold programming(2) 10 uA
tLLPrgm Burst mode transition threshold programming time(2) 2 ms
ADAPTIVE DEADTIME
dVHS/dt Detectable slew rate (falling slope) (2) 0.1 200 V/ns
FAULT RECOVERY
tPauseTimeOut Paused timer (1) 1 s
THERMAL SHUTDOWN
TJ_r Thermal shutdown temperature (1) Temperature rising 125 150 °C
TJ_H Thermal shutdown hysteresis (1) 20 °C
(1) Not tested in production. Validated by characterization
(2) Not tested in production. Validated by design