SLVSIL5A May   2025  – September 2025 UCC25661-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle-by-Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload Protection (OLP)
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
        4. 7.5.3.4 PFC On/Off
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.19 OVP/OTP Pin

The OVP/OTP protects the power stage from over voltage. The OVP/OTP pin is also used for over-temperature protection using a negative temperature coefficient (NTC) thermistor. As the bias winding voltage is the mirror image of the output voltage through the turns ratio of the transformer, pulling up the OVP/OTP pin with a Zener diode is a convenient approach to set the OVP on the primary side. In this design, the nominal output voltage is 12V. To maintain the voltage on VCCP above the UVLO threshold, the bias winding to the secondary side winding turns ratio is 1.5, in other words greater than 12V. Assuming there is a 0.5V drop in the rectifier diodes (Vf) and a further 0.5V drop due to other losses (Vloss), the nominal voltage of the bias winding is calculated using:

Equation 68. VBiasWindingNom=(12+0.5+0.5)×NauxN2=(12+0.5+0.5)×32=19.5V

The desired OVP threshold in this design is 140% of the nominal value. The OVP threshold level (VOVPpos) in UC25661 device is 3.5V.

The required voltage rating of the Zener diode is calculated using:

Equation 69. Vz=(1.4×Vout+Vdrop)×NauxN2−VOVPpos=(1.4×12+0.5+0.5)×32−3.5=23.2V

Assuming actual voltage rating of zener used is 23V, the actual output voltage at which OVP is triggered is

Equation 70. Vout_ovp=(Vz+VOVPpos)×N2Naux−Vdrop=(23+3.5)×23−1=16.67V=139%×Vout

During normal operation, the voltage of the OVP/OTP pin is within the working window from 0.8V to 3.5V. For over temperature protection, pull down the OVP/OTP pin below the OTP threshold of 0.8V.

At room temperature, the OVP/OTP pin voltage is considered as 1.4V. So, at room temperature, the effective resistance value at the OVP/OTP pin is

Equation 71. ROVP/OTP_25=1.4VIOVP_OTP=1.4V100×10−6A=14kΩ
Equation 72. ROVP/OTP_25=Rext×RNTC_25Rext+RNTC_25=14kΩ

where Rext is external resistor that is in parallel with the thermistor. RNTC_25 is the resistance value of the thermistor at room temperature.

For UCC25661EVM-128, over temperature protection is set at the 110°C. Based on the availability and temperature coefficient of the NTCs, choose Equation 73. Refer to the B57371V2474J060 data sheet for more information. RNTC_110 is the resistance of the thermistor at the 110°C.

Equation 73. RNTC_110RNTC_25=0.035263

For OTP trigger, set the OVP/OTP pin voltage below 0.8V.

Equation 74. ROVP/OTP_110=0.8VIOVP_OTP=0.8V100×10−6A=8kΩ
Equation 75. ROVP/OTP_110=Rext×RNTC_110Rext+RNTC_110=8kΩ

From Equation 72, Equation 73, Equation 75, RNTC_25 is 510kΩ and Rext is 14.4kΩ. As a result, RNTC_25 = 470kΩ and Rext=15kΩ. The manufacturer part number for RNTC_25 = 470kΩ is B57371V2474J060.

At room temperature and with new chosen resistors, the OVP/OTP voltage is calculated as:

Equation 76. ROVP/OTP_25×IOVP_OTP=15k×470k15k+470k×100×10−6=1.454V

At 1100C, the OVP/OTP voltage is calculated as:

Equation 77. ROVP/OTP_110×IOVP_OTP=15k×470k×0.03526315k+470k×0.035263×100×10−6=0.78V