SLVUCI2A March   2023  – May 2025 AM68 , AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1 , TPS6594-Q1

 

  1.   1
  2.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  6. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  7. 4Static NVM Settings
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  8. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  9. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  10. 7Impact of NVM Changes
  11. 8References
  12. 9Revision History

4.6 GPIO Settings

These settings detail the default configurations of the GPIO rails. All of these settings can be changed though I2C after startup. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option, see the Digital Signal Descriptions section in TPS6594-Q1 data sheet.

Table 4-6 GPIO NVM Settings
Register Name Field Name TPS6594
Value Description
GPIO1_CONF GPIO1_OD 0x0 Push-pull output
GPIO1_DIR 0x0 Input
GPIO1_SEL 0x1 SCL_I2C2/CS_SPI
GPIO1_PU_SEL 0x0 Pull-down resistor selected
GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization.
GPIO2_CONF GPIO2_OD 0x0 Push-pull output
GPIO2_DIR 0x0 Input
GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI
GPIO2_PU_SEL 0x0 Pull-down resistor selected
GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization.
GPIO3_CONF GPIO3_OD 0x0 Push-pull output
GPIO3_DIR 0x0 Input
GPIO3_SEL 0x2 NERR_SOC
GPIO3_PU_SEL 0x0 Pull-down resistor selected
GPIO3_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO3_DEGLITCH_EN 0x1 8 us deglitch time.
GPIO4_CONF GPIO4_OD 0x0 Push-pull output
GPIO4_DIR 0x0 Input
GPIO4_SEL 0x6 LP_WKUP1
GPIO4_PU_SEL 0x0 Pull-down resistor selected
GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO4_DEGLITCH_EN 0x1 8 us deglitch time.
GPIO5_CONF GPIO5_OD 0x0 Push-pull output
GPIO5_DIR 0x1 Output
GPIO5_SEL 0x0 GPIO5
GPIO5_PU_SEL 0x0 Pull-down resistor selected
GPIO5_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO5_DEGLITCH_EN 0x0 No deglitch, only synchronization.
GPIO6_CONF GPIO6_OD 0x1 Open-drain output
GPIO6_DIR 0x1 Output
GPIO6_SEL 0x0 GPIO6
GPIO6_PU_SEL 0x0 Pull-down resistor selected
GPIO6_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO6_DEGLITCH_EN 0x0 No deglitch, only synchronization.
GPIO7_CONF GPIO7_OD 0x0 Push-pull output
GPIO7_DIR 0x0 Input
GPIO7_SEL 0x1 NERR_MCU
GPIO7_PU_SEL 0x0 Pull-down resistor selected
GPIO7_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO7_DEGLITCH_EN 0x1 8 us deglitch time.
GPIO8_CONF GPIO8_OD 0x0 Push-pull output
GPIO8_DIR 0x0 Input
GPIO8_SEL 0x0 GPIO8
GPIO8_PU_SEL 0x0 Pull-down resistor selected
GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor.
GPIO8_DEGLITCH_EN 0x1 8 us deglitch time.
GPIO9_CONF GPIO9_OD 0x0 Push-pull output
GPIO9_DIR 0x0 Input
GPIO9_SEL 0x2 DISABLE_WDOG
GPIO9_PU_SEL 0x0 Pull-down resistor selected
GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor.
GPIO9_DEGLITCH_EN 0x0 No deglitch, only synchronization.
GPIO10_CONF GPIO10_OD 0x0 Push-pull output
GPIO10_DIR 0x0 Input
GPIO10_SEL 0x0 GPIO10
GPIO10_PU_SEL 0x0 Pull-down resistor selected
GPIO10_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO10_DEGLITCH_EN 0x1 8 us deglitch time.
GPIO11_CONF GPIO11_OD 0x1 Open-drain output
GPIO11_DIR 0x1 Output
GPIO11_SEL 0x2 NRSTOUT_SOC
GPIO11_PU_SEL 0x0 Pull-down resistor selected
GPIO11_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
GPIO11_DEGLITCH_EN 0x0 No deglitch, only synchronization.
NPWRON_CONF NPWRON_SEL 0x0 ENABLE
ENABLE_PU_SEL 0x0 Pull-down resistor selected
ENABLE_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor.
ENABLE_DEGLITCH_EN 0x0 No deglitch, only synchronization.
ENABLE_POL 0x0 Active high
NRSTOUT_OD 0x1 Open-drain output
GPIO_OUT_1 GPIO1_OUT 0x0 Low
GPIO2_OUT 0x0 Low
GPIO3_OUT 0x0 Low
GPIO4_OUT 0x0 Low
GPIO5_OUT 0x0 Low
GPIO6_OUT 0x0 Low
GPIO7_OUT 0x0 Low
GPIO8_OUT 0x0 Low
GPIO_OUT_2 GPIO9_OUT 0x0 Low
GPIO10_OUT 0x0 Low
GPIO11_OUT 0x0 Low