SLVUCI2A March   2023  – May 2025 AM68 , AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1 , TPS6594-Q1

 

  1.   1
  2.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  6. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  7. 4Static NVM Settings
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  8. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  9. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  10. 7Impact of NVM Changes
  11. 8References
  12. 9Revision History

3.2 Achieving up to ASIL-D System Requirements

For ASIL-C or ASIL-D systems, the following features in addition to the ones described in Section 3.1 can be used:

  • PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
  • PMIC current monitoring on all output power rails
  • SoC error monitoring
  • Switch short-to-ground detection on BUCK regulator pins (SW_Bx)
  • Residual Voltage Monitoring
  • Read-back of Logic Output Pins
    • nINT of the PMIC
    • nRSTOUT and nRSTOUT_SOC of the PMIC

The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594133A.

GPIO_3 of the TPS6594133A PMIC is configured as the SoC error signal monitor. Similar to the MCU error signal monitor, this feature is enabled through I2C using the ESM_SOC_EN register bit. The SoC reset functionality is supported through the connection of GPIO_11 on the TPS6594133A, configured as nRSTOUT_SoC, to the PORz pin of the processor.

Table 3-1 System Level Safety Features
ASIL-B ASIL-D
Safety Monitoring Processor External SW Wdog INTn Safety MCU Processing ESM
Safety MCU Reset		 Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring SoC Main Processing ESM IO Read-Back Feature
SoC: MCU Island
R5 Cores		 PMIC: Q&A Watchdog and I2C2 PMIC : nINT PMIC: nERR_MCU connected to SOC: MCU_SAFETY_ERRz
PMIC: nRSTOUT connected to MCU_PORz_1V8		 PMIC: ENDRV PMIC: VSYS_SENSE -OV with Safety FET OVPGDRV with VCCA OV & UV and SoC (VMON1) -UV PMIC: nERR_SoC connected to SOC: SOC_SAFETY_ERRz PMIC: nINT, nRSTOUT, nRSTOUT_SOC
Table 3-2 Power Monitoring Safety Features
ASIL-B ASIL-D Adds
Device Power Resource PDN Power Rail Safe State Power Group1 Supply Voltage Monitoring Supply Current Monitoring Residual Voltage Monitoring
TPS6594133A-Q1 (PMIC) BUCK1-2 VDD_DDR_1V1 MCU PMIC - OV and UV2 PMIC -CM2 PMIC -RVM2
BUCK3 VDD_RAM_0V85 SOC PMIC - OV and UV PMIC -CM PMIC -RVM
BUCK4 VDD_IO_1V8 SOC PMIC - OV and UV PMIC -CM PMIC -RVM
BUCK5 VDD_MCU_0V85 MCU PMIC - OV and UV PMIC -CM PMIC -RVM
LDO1 VDD_MCUIO_1V8 MCU PMIC - OV and UV PMIC -CM PMIC -RVM
LDO2 VDD_MCUIO_3V3 MCU PMIC - OV and UV PMIC -CM PMIC -RVM
LDO3 VDA_DLL_0V8 SOC PMIC - OV and UV PMIC -CM PMIC -RVM
LDO4 VDA_MCU_1V8 MCU PMIC - OV and UV PMIC -CM PMIC -RVM
TPS22965-Q1 LDSW- A VDD_IO_3V3 SOC 6 Discrete SVS-A NA45
TPS22965-Q1 LDSW- B VDD_MCU_GPIORET_3V3 MCU 6 Discrete SVS-B 8 NA
HCPS-A HCPS-A VDD_CPU_AVS SOC 6 Discrete SVS-A BUCK-OC
HCPS-B HCPS-B VDD_CORE_0V8 MCU 6 Discrete SVS-A BUCK-OC
TPS74501P-Q1 LDO-A VDA_PLL_1V8 SOC 6 Discrete SVS-A LDO-OCP 7
TPS74501P-Q1 LDO-B VDA_PHY_1V8 SOC 6 Discrete SVS-A LDO-OCP 7
TPS74501P-Q1 LDO-C VDD_MCU_GPIORET_0V8 MCU 6 Discrete SVS-B 8 LDO-OCP 7
TPS74501P-Q1 LDO-D VDD1_DDR_1V8 SOC 6 Discrete SVS-A LDO-OCP 7
TLV7103318-Q1 LDO-E VDD_SD_DV None NA 3 NA 3
TLV73333P-Q1 LDO-F VDA_USB_3V3 None NA 3 NA 3
TLV73318P-Q1 LDO-G VPP_EFUSE_1V8 None NA 3 NA 3
  1. Rail Group settings for the TPS6594133A-Q1 is found in Table 4-7.
  2. Power rail VDD_DDR_1V1 is safety critical but do not required direct voltage or current monitoring since other means are available (for example, SoC internal timeout gaskets and ECC checkers) provide diagnostic coverage to detect faults in the DDR voltage.
  3. Power rails VDD_SD_DV, VPP_EFUSE_1V8, and VDA_USB_3V38 are not safety critical.
  4. Power rail VDD_IO_3V3 is typically not safety critical since other means are available (for example, black-channel checkers) to provide diagnostic coverage to detect faults in SoC signaling interfaces (for example, CAN, UART, and SPI).
  5. If an SoC GPIO control signal is used in a safety critical interface, then adding voltage and current monitoring to specific VIO power rail can be needed per customer's end product design.
  6. For power resources not provided by the PMIC, the power group is determined by discrete SVS voltage monitor.
  7. These discrete power resource feature built-in over current protection and a power good signal that can be routed back to the PMIC.
  8. Discrete SVS-B is unnecessary in systems without LDSW-B and LDO-C.