SLVUCI2A March   2023  – May 2025 AM68 , AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1 , TPS6594-Q1

 

  1.   1
  2.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  6. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  7. 4Static NVM Settings
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  8. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  9. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  10. 7Impact of NVM Changes
  11. 8References
  12. 9Revision History

5.1 Configured States

For the PDNs described in this user guide, the PMIC has the following five configured power states:

  • Standby
  • Wait4Enable
  • Active
  • MCU Only
  • Pwr SoC Error
  • Retention (GPIO and DDR)

In Figure 5-1, the configured PDN power states are shown, along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6594-Q1 data sheet, see Section 8.

TPS6594-Q1 Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions Figure 5-1 Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions

When the PMIC transitions from the FSM to the PFSM, several initialization instructions are performed to disable the residual voltage checks on both the BUCK and LDO regulators. Additionally, the FIRST_STARTUP_DONE bit is set and VCCA OV and UV masks are cleared (which are set in the static configurations, Table 4-8). After these instructions are executed the PMICs wait for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below:

    STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the Section 5.3.2 sequence description.
    WAIT4ENABLE The WAIT4ENABLE state is entered when an error occurs and the PMIC transitions out of the PFSM mission states and into the FSM states. When the device returns from the FSM state the to PFSM the first state is represented by WAIT4ENABLE with all of the resources powered down and EN_DRV forced low. The sequence Section 5.3.1 is performed before the PMIC leaves the PFSM and enters the FSM state SAFE_RECOVERY.
    ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized in both MCU and Main processor sections. Refer to the Section 5.3.8 sequence description.
    MCU_ONLY The PMIC is powered by a valid supply. Only the power resources assigned to the MCU Safety Island are on. Refer to the Section 5.3.7 sequence description.
    Pwr SoC Error The PMIC is powered by a valid supply. Only the power resources assigned to the MCU Safety Island are on. Refer to the Section 5.3.5 sequence description. The only active trigger is 'B', requiring the PMICs to return to the MCU_ONLY mode. The return to MCU_ONLY mode and eventually ACTIVE mode is only recommended after the interrupts which caused the SOC_PWR_ERROR have been cleared.
    Retention The PMIC is powered by a valid supply. Only the power resources assigned to the retention rails are on or in LPM depending on the specific resource setting. If a given resource is maintained active, then all linked subsystems are automatically maintained active. ENABLE_DRV bit is cleared by the device in this state. If the I2C_5 bit is set high, the PMIC enters GPIO retention state. If the I2C_7 bit is set high, the PMIC enters DDR retention state. These bits need to be set before a trigger for the retention state occurs. Refer to the Section 5.3.9 sequence description.