SPRACP3D November 2019 – August 2026 AWR6843 , AWR6843AOP , IWR1443 , IWR1642 , IWR6443 , IWR6843 , IWR6843AOP
One method for reducing 14.4GHz and 28.8GHz spurs is by duty cycling the APLL. This is done by placing the APLL in power down mode. This can be performed by first treating needed system clocks and then disabling the APLL. The RFAFE and APLL power down can be completed with the GPADC either enabled or disabled depending on user needs. The AFE and the APLL is then re-enabled prior to chirping.
APLL duty cycling does not totally eliminate the spur, but can greatly reduce the average emissions caused by the APLL. APLL duty cycling is a preferable first option to more aggressive options like RTRIM changes. This is because changes to RTRIM can cause instability in the synthesizer and must only be performed if absolutely needed. For more information on APLL duty cycling, see the Software Strategies to Achieve Power Optimizations in TI Millimeter Wave Sensors application note.
Figure 6-5 Analog Domain Power States