The above workaround option requires extra software bandwidth to deal with such corner case, while another option with the configurable logic block (CLB) is hardware based and more straightforward. The basic idea is to use CLB to monitor the on time of the specific ePWM output, and clamp it within the expected duty cycle if the above corner case is going to occur.

As shown in Figure 2-10, with ePWM1A as an example, the output of the AQ submodule of ePWM1 is used for the CLB input signals, and COUNTER0 is used to count the on time of ePWM1A. FSM0 will provide the clamped signals, where FSM0 e0 refers to the rising edge of EPWM1A[AQ], and FSM0 e1 refers to the COUNTER0 match1 event. Thus, the actual EPWM1A[AQ] signal is the AND logic with FSM0 s0.

Based on such scheme, every time the multiple ePWM registers are updated, the match1_val register of COUNTER0 is also updated with the clamped duty cycle, which is the CMPA value in Section 2.3.2.1. In this way, the ePWM output can be always ensured in a safe status. The above configuration has been validated with the F280049 control card, as shown in Figure 2-11, where the duty cycle of ePWM1A is initially set with 50%, and it is finally clamped to 30% by CLB.