SPRUJB3 User guide

SPRUJB3C March 2024 – November 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

4.14.4.2 TIMER Integration

Table 4-387 TIMER Module Allocations

Instance	MAIN	MCU	WKUP
TIMER0	✓
TIMER1	✓
TIMER2	✓
TIMER3	✓
TIMER4	✓
TIMER5	✓
TIMER6	✓
TIMER7	✓
MCU_TIMER0		✓
MCU_TIMER1		✓
MCU_TIMER2		✓
MCU_TIMER3		✓
WKUP_TIMER0			✓
WKUP_TIMER1			✓

Table 4-388 Integration Attributes for TIMER

Module Instance	Power Sleep Controller	Power Domain	Module Domain	Index	Default	Controllable	Dependencies
TIMER0	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER1	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER2	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER3	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER4	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER5	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER6	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
TIMER7	PSC0	GP_CORE	LPSC_main_ip	34	ON	YES	LPSC_main_dm2main_infra_iso
MCU_TIMER0	WKUP_PSC0	PD_MCUSS	LPSC_MCU_common	9	ON	YES	LPSC_DM2safe_ISO
MCU_TIMER1	WKUP_PSC0	PD_MCUSS	LPSC_MCU_common	9	ON	YES	LPSC_DM2safe_ISO
MCU_TIMER2	WKUP_PSC0	PD_MCUSS	LPSC_MCU_common	9	ON	YES	LPSC_DM2safe_ISO
MCU_TIMER3	WKUP_PSC0	PD_MCUSS	LPSC_MCU_common	9	ON	YES	LPSC_DM2safe_ISO
WKUP_TIMER0	PSC0	GP_CORE	LPSC_main_alwayson	0	ON	NO
WKUP_TIMER1	PSC0	GP_CORE	LPSC_main_alwayson	0	ON	NO

Table 4-389 Clock Integration for TIMER

Module Instance	Module Clock Input	Source Clock	Source Control Register	Description
TIMER0	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER0	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=0	functional clock
TIMER0	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=0	functional clock
TIMER0	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER0	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER0	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER0	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER0	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER0	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=10	functional clock
TIMER0	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=11	functional clock
TIMER0	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=2	functional clock
TIMER0	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=3	functional clock
TIMER0	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=4	functional clock
TIMER0	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=5	functional clock
TIMER0	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=7	functional clock
TIMER0	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=8	functional clock
TIMER0	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL[3:0]=9	functional clock
TIMER1	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER1	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=0	functional clock
TIMER1	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=0	functional clock
TIMER1	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER1	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER1	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER1	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER1	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER1	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=10	functional clock
TIMER1	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=11	functional clock
TIMER1	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=2	functional clock
TIMER1	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=3	functional clock
TIMER1	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=4	functional clock
TIMER1	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=5	functional clock
TIMER1	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=7	functional clock
TIMER1	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=8	functional clock
TIMER1	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL[3:0]=9	functional clock
TIMER1	FCLK	TIMER0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER1_CTRL[8:8]=1	functional clock
TIMER2	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER2	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=0	functional clock
TIMER2	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=0	functional clock
TIMER2	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER2	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER2	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER2	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER2	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER2	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=10	functional clock
TIMER2	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=11	functional clock
TIMER2	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=2	functional clock
TIMER2	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=3	functional clock
TIMER2	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=4	functional clock
TIMER2	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=5	functional clock
TIMER2	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=7	functional clock
TIMER2	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=8	functional clock
TIMER2	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL[3:0]=9	functional clock
TIMER3	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER3	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=0	functional clock
TIMER3	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=0	functional clock
TIMER3	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER3	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER3	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER3	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER3	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER3	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=10	functional clock
TIMER3	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=11	functional clock
TIMER3	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=2	functional clock
TIMER3	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=3	functional clock
TIMER3	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=4	functional clock
TIMER3	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=5	functional clock
TIMER3	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=7	functional clock
TIMER3	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=8	functional clock
TIMER3	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL[3:0]=9	functional clock
TIMER3	FCLK	TIMER2 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER3_CTRL[8:8]=1	functional clock
TIMER4	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER4	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=0	functional clock
TIMER4	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=0	functional clock
TIMER4	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER4	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER4	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER4	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER4	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER4	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=10	functional clock
TIMER4	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=11	functional clock
TIMER4	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=2	functional clock
TIMER4	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=3	functional clock
TIMER4	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=4	functional clock
TIMER4	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=5	functional clock
TIMER4	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=7	functional clock
TIMER4	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=8	functional clock
TIMER4	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL[3:0]=9	functional clock
TIMER5	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER5	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=0	functional clock
TIMER5	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=0	functional clock
TIMER5	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER5	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER5	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER5	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER5	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER5	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=10	functional clock
TIMER5	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=11	functional clock
TIMER5	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=2	functional clock
TIMER5	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=3	functional clock
TIMER5	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=4	functional clock
TIMER5	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=5	functional clock
TIMER5	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=7	functional clock
TIMER5	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=8	functional clock
TIMER5	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL[3:0]=9	functional clock
TIMER5	FCLK	TIMER4 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER5_CTRL[8:8]=1	functional clock
TIMER6	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER6	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=0	functional clock
TIMER6	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=0	functional clock
TIMER6	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER6	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER6	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER6	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER6	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER6	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=10	functional clock
TIMER6	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=11	functional clock
TIMER6	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=2	functional clock
TIMER6	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=3	functional clock
TIMER6	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=4	functional clock
TIMER6	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=5	functional clock
TIMER6	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=7	functional clock
TIMER6	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=8	functional clock
TIMER6	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL[3:0]=9	functional clock
TIMER7	ICLK	MAIN_SYSCLK0/4		interface clock
TIMER7	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=0	functional clock
TIMER7	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=0	functional clock
TIMER7	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
TIMER7	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER7	FCLK	HFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
TIMER7	FCLK	CLK_32K_RC	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
TIMER7	FCLK	LFOSC0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=1 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
TIMER7	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=10	functional clock
TIMER7	FCLK	CPSW0 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=11	functional clock
TIMER7	FCLK	MAIN_PLL0_HSDIV7_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=2	functional clock
TIMER7	FCLK	CLK_12M_RC	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=3	functional clock
TIMER7	FCLK	MCU_EXT_REFCLK0	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=4	functional clock
TIMER7	FCLK	EXT_REFCLK1	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=5	functional clock
TIMER7	FCLK	CP_GEMAC_CPTS_REF_CLK	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=7	functional clock
TIMER7	FCLK	MAIN_PLL1_HSDIV3_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=8	functional clock
TIMER7	FCLK	MAIN_PLL2_HSDIV6_CLKOUT	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=0 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL[3:0]=9	functional clock
TIMER7	FCLK	TIMER6 (INSTANCE)	MAIN_CTRL_MMR_CFG0_TIMER7_CTRL[8:8]=1	functional clock
MCU_TIMER0	ICLK	MCU_SYSCLK0/4		interface clock
MCU_TIMER0	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=0	functional clock
MCU_TIMER0	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=0	functional clock
MCU_TIMER0	FCLK	MCU_SYSCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=1	functional clock
MCU_TIMER0	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=2	functional clock
MCU_TIMER0	FCLK	MCU_PLL0_HSDIV5_CLKOUT	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=3	functional clock
MCU_TIMER0	FCLK	MCU_EXT_REFCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=4	functional clock
MCU_TIMER0	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
MCU_TIMER0	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER0	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER0	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
MCU_TIMER0	FCLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
MCU_TIMER0	FCLK	CPSW0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=6	functional clock
MCU_TIMER0	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL[2:0]=7	functional clock
MCU_TIMER1	ICLK	MCU_SYSCLK0/4		interface clock
MCU_TIMER1	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=0	functional clock
MCU_TIMER1	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=0	functional clock
MCU_TIMER1	FCLK	MCU_SYSCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=1	functional clock
MCU_TIMER1	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=2	functional clock
MCU_TIMER1	FCLK	MCU_PLL0_HSDIV5_CLKOUT	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=3	functional clock
MCU_TIMER1	FCLK	MCU_EXT_REFCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=4	functional clock
MCU_TIMER1	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
MCU_TIMER1	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER1	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER1	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
MCU_TIMER1	FCLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
MCU_TIMER1	FCLK	CPSW0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=6	functional clock
MCU_TIMER1	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL[2:0]=7	functional clock
MCU_TIMER1	FCLK	MCU_TIMER0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL[8:8]=1	functional clock
MCU_TIMER2	ICLK	MCU_SYSCLK0/4		interface clock
MCU_TIMER2	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=0	functional clock
MCU_TIMER2	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=0	functional clock
MCU_TIMER2	FCLK	MCU_SYSCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=1	functional clock
MCU_TIMER2	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=2	functional clock
MCU_TIMER2	FCLK	MCU_PLL0_HSDIV5_CLKOUT	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=3	functional clock
MCU_TIMER2	FCLK	MCU_EXT_REFCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=4	functional clock
MCU_TIMER2	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
MCU_TIMER2	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER2	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER2	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
MCU_TIMER2	FCLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
MCU_TIMER2	FCLK	CPSW0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=6	functional clock
MCU_TIMER2	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL[2:0]=7	functional clock
MCU_TIMER3	ICLK	MCU_SYSCLK0/4		interface clock
MCU_TIMER3	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=0	functional clock
MCU_TIMER3	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=0	functional clock
MCU_TIMER3	FCLK	MCU_SYSCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=1	functional clock
MCU_TIMER3	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=2	functional clock
MCU_TIMER3	FCLK	MCU_PLL0_HSDIV5_CLKOUT	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=3	functional clock
MCU_TIMER3	FCLK	MCU_EXT_REFCLK0	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=4	functional clock
MCU_TIMER3	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
MCU_TIMER3	FCLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER3	FCLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
MCU_TIMER3	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
MCU_TIMER3	FCLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
MCU_TIMER3	FCLK	CPSW0 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=6	functional clock
MCU_TIMER3	FCLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=0 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL[2:0]=7	functional clock
MCU_TIMER3	FCLK	MCU_TIMER2 (INSTANCE)	MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL[8:8]=1	functional clock
WKUP_TIMER0	ICLK	DM_CLK/2		interface clock
WKUP_TIMER0	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=0	functional clock
WKUP_TIMER0	FCLK	HFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=0	functional clock
WKUP_TIMER0	FCLK	DM_CLK	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=1	functional clock
WKUP_TIMER0	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=2	functional clock
WKUP_TIMER0	FCLK	MCU_PLL0_HSDIV5_CLKOUT	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=3	functional clock
WKUP_TIMER0	FCLK	MCU_EXT_REFCLK0	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=4	functional clock
WKUP_TIMER0	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
WKUP_TIMER0	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
WKUP_TIMER0	FCLK	HFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
WKUP_TIMER0	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
WKUP_TIMER0	FCLK	LFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
WKUP_TIMER0	FCLK	CPSW0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=6	functional clock
WKUP_TIMER0	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER0_CLKSEL[2:0]=7	functional clock
WKUP_TIMER1	ICLK	DM_CLK/2		interface clock
WKUP_TIMER1	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=0	functional clock
WKUP_TIMER1	FCLK	HFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=0	functional clock
WKUP_TIMER1	FCLK	DM_CLK	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=1	functional clock
WKUP_TIMER1	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=2	functional clock
WKUP_TIMER1	FCLK	MCU_PLL0_HSDIV5_CLKOUT	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=3	functional clock
WKUP_TIMER1	FCLK	MCU_EXT_REFCLK0	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=4	functional clock
WKUP_TIMER1	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	functional clock
WKUP_TIMER1	FCLK	CLK_12M_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
WKUP_TIMER1	FCLK	HFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	functional clock
WKUP_TIMER1	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	functional clock
WKUP_TIMER1	FCLK	LFOSC0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=5 MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	functional clock
WKUP_TIMER1	FCLK	CPSW0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=6	functional clock
WKUP_TIMER1	FCLK	CLK_32K_RC	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=0 WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CLKSEL[2:0]=7	functional clock
WKUP_TIMER1	FCLK	WKUP_TIMER0 (INSTANCE)	WKUP_CTRL_MMR_CFG0_WKUP_TIMER1_CTRL[8:8]=1	functional clock

Table 4-390 Reset Integration for TIMER

Module Instance	Source	Description
TIMER0	PSC0	TIMER0 reset
TIMER1	PSC0	TIMER1 reset
TIMER2	PSC0	TIMER2 reset
TIMER3	PSC0	TIMER3 reset
TIMER4	PSC0	TIMER4 reset
TIMER5	PSC0	TIMER5 reset
TIMER6	PSC0	TIMER6 reset
TIMER7	PSC0	TIMER7 reset
MCU_TIMER0	WKUP_PSC0	MCU_TIMER0 reset
MCU_TIMER1	WKUP_PSC0	MCU_TIMER1 reset
MCU_TIMER2	WKUP_PSC0	MCU_TIMER2 reset
MCU_TIMER3	WKUP_PSC0	MCU_TIMER3 reset
WKUP_TIMER0	PSC0	WKUP_TIMER0 reset
WKUP_TIMER1	PSC0	WKUP_TIMER1 reset

Table 4-391 Hardware Requests for TIMER

Module Instance	Module Interrupt Signal	Destination Interrupt Input	Destination	Description	Type
TIMER0	TIMER0_intr_pend_0	GICSS0_spi_152	GICSS0	TIMER0 interrupt request	level
TIMER0	TIMER0_intr_pend_0	R5FSS0_CORE0_intr_24	R5FSS0_CORE0	TIMER0 interrupt request	level
TIMER0	TIMER0_intr_pend_0	C7X256V0_CLEC_gic_spi_152	C7X256V0_CLEC	TIMER0 interrupt request	level
TIMER0	TIMER0_intr_pend_0	C7X256V1_CLEC_gic_spi_152	C7X256V1_CLEC	TIMER0 interrupt request	level
TIMER0	TIMER0_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_162	MAIN_GPIOMUX_INTROUTER0	TIMER0 interrupt request	pulse
TIMER0	TIMER0_timer_pwm_0	TIMESYNC_EVENT_INTROUTER0_in_0	TIMESYNC_EVENT_INTROUTER0	TIMER0 interrupt request	pulse
TIMER1	TIMER1_intr_pend_0	GICSS0_spi_153	GICSS0	TIMER1 interrupt request	level
TIMER1	TIMER1_intr_pend_0	R5FSS0_CORE0_intr_25	R5FSS0_CORE0	TIMER1 interrupt request	level
TIMER1	TIMER1_intr_pend_0	C7X256V0_CLEC_gic_spi_153	C7X256V0_CLEC	TIMER1 interrupt request	level
TIMER1	TIMER1_intr_pend_0	C7X256V1_CLEC_gic_spi_153	C7X256V1_CLEC	TIMER1 interrupt request	level
TIMER1	TIMER1_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_163	MAIN_GPIOMUX_INTROUTER0	TIMER1 interrupt request	pulse
TIMER1	TIMER1_timer_pwm_0	TIMESYNC_EVENT_INTROUTER0_in_1	TIMESYNC_EVENT_INTROUTER0	TIMER1 interrupt request	pulse
TIMER2	TIMER2_intr_pend_0	GICSS0_spi_154	GICSS0	TIMER2 interrupt request	level
TIMER2	TIMER2_intr_pend_0	R5FSS0_CORE0_intr_26	R5FSS0_CORE0	TIMER2 interrupt request	level
TIMER2	TIMER2_intr_pend_0	C7X256V0_CLEC_gic_spi_154	C7X256V0_CLEC	TIMER2 interrupt request	level
TIMER2	TIMER2_intr_pend_0	C7X256V1_CLEC_gic_spi_154	C7X256V1_CLEC	TIMER2 interrupt request	level
TIMER2	TIMER2_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_164	MAIN_GPIOMUX_INTROUTER0	TIMER2 interrupt request	pulse
TIMER2	TIMER2_timer_pwm_0	TIMESYNC_EVENT_INTROUTER0_in_2	TIMESYNC_EVENT_INTROUTER0	TIMER2 interrupt request	pulse
TIMER3	TIMER3_intr_pend_0	GICSS0_spi_155	GICSS0	TIMER3 interrupt request	level
TIMER3	TIMER3_intr_pend_0	R5FSS0_CORE0_intr_27	R5FSS0_CORE0	TIMER3 interrupt request	level
TIMER3	TIMER3_intr_pend_0	C7X256V0_CLEC_gic_spi_155	C7X256V0_CLEC	TIMER3 interrupt request	level
TIMER3	TIMER3_intr_pend_0	C7X256V1_CLEC_gic_spi_155	C7X256V1_CLEC	TIMER3 interrupt request	level
TIMER3	TIMER3_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_165	MAIN_GPIOMUX_INTROUTER0	TIMER3 interrupt request	pulse
TIMER3	TIMER3_timer_pwm_0	TIMESYNC_EVENT_INTROUTER0_in_3	TIMESYNC_EVENT_INTROUTER0	TIMER3 interrupt request	pulse
TIMER4	TIMER4_intr_pend_0	GICSS0_spi_156	GICSS0	TIMER4 interrupt request	level
TIMER4	TIMER4_intr_pend_0	R5FSS0_CORE0_intr_28	R5FSS0_CORE0	TIMER4 interrupt request	level
TIMER4	TIMER4_intr_pend_0	C7X256V0_CLEC_gic_spi_156	C7X256V0_CLEC	TIMER4 interrupt request	level
TIMER4	TIMER4_intr_pend_0	C7X256V1_CLEC_gic_spi_156	C7X256V1_CLEC	TIMER4 interrupt request	level
TIMER4	TIMER4_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_166	MAIN_GPIOMUX_INTROUTER0	TIMER4 interrupt request	pulse
TIMER5	TIMER5_intr_pend_0	GICSS0_spi_157	GICSS0	TIMER5 interrupt request	level
TIMER5	TIMER5_intr_pend_0	R5FSS0_CORE0_intr_29	R5FSS0_CORE0	TIMER5 interrupt request	level
TIMER5	TIMER5_intr_pend_0	C7X256V0_CLEC_gic_spi_157	C7X256V0_CLEC	TIMER5 interrupt request	level
TIMER5	TIMER5_intr_pend_0	C7X256V1_CLEC_gic_spi_157	C7X256V1_CLEC	TIMER5 interrupt request	level
TIMER5	TIMER5_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_167	MAIN_GPIOMUX_INTROUTER0	TIMER5 interrupt request	pulse
TIMER6	TIMER6_intr_pend_0	GICSS0_spi_158	GICSS0	TIMER6 interrupt request	level
TIMER6	TIMER6_intr_pend_0	R5FSS0_CORE0_intr_34	R5FSS0_CORE0	TIMER6 interrupt request	level
TIMER6	TIMER6_intr_pend_0	C7X256V0_CLEC_gic_spi_158	C7X256V0_CLEC	TIMER6 interrupt request	level
TIMER6	TIMER6_intr_pend_0	C7X256V1_CLEC_gic_spi_158	C7X256V1_CLEC	TIMER6 interrupt request	level
TIMER6	TIMER6_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_168	MAIN_GPIOMUX_INTROUTER0	TIMER6 interrupt request	pulse
TIMER7	TIMER7_intr_pend_0	GICSS0_spi_159	GICSS0	TIMER7 interrupt request	level
TIMER7	TIMER7_intr_pend_0	R5FSS0_CORE0_intr_35	R5FSS0_CORE0	TIMER7 interrupt request	level
TIMER7	TIMER7_intr_pend_0	C7X256V0_CLEC_gic_spi_159	C7X256V0_CLEC	TIMER7 interrupt request	level
TIMER7	TIMER7_intr_pend_0	C7X256V1_CLEC_gic_spi_159	C7X256V1_CLEC	TIMER7 interrupt request	level
TIMER7	TIMER7_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_169	MAIN_GPIOMUX_INTROUTER0	TIMER7 interrupt request	pulse
MCU_TIMER0	MCU_TIMER0_intr_pend_0	MCU_R5FSS0_CORE0_cpu0_intr_28	MCU_R5FSS0_CORE0	MCU_TIMER0 interrupt request	level
MCU_TIMER0	MCU_TIMER0_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_170	MAIN_GPIOMUX_INTROUTER0	MCU_TIMER0 interrupt request	pulse
MCU_TIMER1	MCU_TIMER1_intr_pend_0	MCU_R5FSS0_CORE0_cpu0_intr_29	MCU_R5FSS0_CORE0	MCU_TIMER1 interrupt request	level
MCU_TIMER1	MCU_TIMER1_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_171	MAIN_GPIOMUX_INTROUTER0	MCU_TIMER1 interrupt request	pulse
MCU_TIMER2	MCU_TIMER2_intr_pend_0	MCU_R5FSS0_CORE0_cpu0_intr_138	MCU_R5FSS0_CORE0	MCU_TIMER2 interrupt request	level
MCU_TIMER2	MCU_TIMER2_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_172	MAIN_GPIOMUX_INTROUTER0	MCU_TIMER2 interrupt request	pulse
MCU_TIMER3	MCU_TIMER3_intr_pend_0	MCU_R5FSS0_CORE0_cpu0_intr_139	MCU_R5FSS0_CORE0	MCU_TIMER3 interrupt request	level
MCU_TIMER3	MCU_TIMER3_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_173	MAIN_GPIOMUX_INTROUTER0	MCU_TIMER3 interrupt request	pulse
WKUP_TIMER0	WKUP_TIMER0_intr_pend_0	WKUP_R5FSS0_CORE0_intr_138	WKUP_R5FSS0_CORE0	WKUP_TIMER0 interrupt request	level
WKUP_TIMER0	WKUP_TIMER0_timer_clkstop_wakeup_0	WKUP_R5FSS0_CORE0_intr_28	WKUP_R5FSS0_CORE0	WKUP_TIMER0 interrupt request	level
WKUP_TIMER0	WKUP_TIMER0_timer_clkstop_wakeup_0	WKUP_DEEPSLEEP_SOURCES0_Isam62_dm_wakeup_deepsleep_sources_5	WKUP_DEEPSLEEP_SOURCES0	WKUP_TIMER0 interrupt request	level
WKUP_TIMER0	WKUP_TIMER0_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_174	MAIN_GPIOMUX_INTROUTER0	WKUP_TIMER0 interrupt request	pulse
WKUP_TIMER1	WKUP_TIMER1_intr_pend_0	WKUP_R5FSS0_CORE0_intr_139	WKUP_R5FSS0_CORE0	WKUP_TIMER1 interrupt request	level
WKUP_TIMER1	WKUP_TIMER1_timer_clkstop_wakeup_0	WKUP_R5FSS0_CORE0_intr_29	WKUP_R5FSS0_CORE0	WKUP_TIMER1 interrupt request	level
WKUP_TIMER1	WKUP_TIMER1_timer_clkstop_wakeup_0	WKUP_DEEPSLEEP_SOURCES0_Isam62_dm_wakeup_deepsleep_sources_6	WKUP_DEEPSLEEP_SOURCES0	WKUP_TIMER1 interrupt request	level
WKUP_TIMER1	WKUP_TIMER1_timer_pwm_0	MAIN_GPIOMUX_INTROUTER0_in_175	MAIN_GPIOMUX_INTROUTER0	WKUP_TIMER1 interrupt request	pulse