SPRUJF7 March   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
      2. 1.1.1 Sitara MCU+ Academy
      3. 1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Setup
    3. 2.3  Power Requirements
      1. 2.3.1 Power Tree
      2. 2.3.2 Power Sequence
    4. 2.4  Header Information
      1. 2.4.1 Baseboard Headers (J1, J2, J3)
      2. 2.4.2 HSEC Pinout
      3. 2.4.3 XDS Debug Header (J4)
      4. 2.4.4 FSI Header
      5. 2.4.5 OSPI Expansion Connector
      6. 2.4.6 Ethernet Add-on Board Connector
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  GPIO Mapping
    8. 2.8  Interfaces
      1. 2.8.1 USB
      2. 2.8.2 UART
      3. 2.8.3 FSI
      4. 2.8.4 OSPI
      5. 2.8.5 Ethernet
        1. 2.8.5.1 RGMII
        2. 2.8.5.2 PRU-ICSS
          1. 2.8.5.2.1 On-Board PHY
          2. 2.8.5.2.2 Ethernet Add-on Board
      6. 2.8.6 I2C
      7. 2.8.7 SPI
      8. 2.8.8 TMDSHSECDOCK-AM263 Peripherals
        1. 2.8.8.1 ADC/DAC
        2. 2.8.8.2 MCAN
        3. 2.8.8.3 LIN1
        4. 2.8.8.4 JTAG
        5. 2.8.8.5 GPIO
    9. 2.9  Debug Information
    10. 2.10 Test Points
    11. 2.11 Assembly Instructions
    12. 2.12 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References
    1. 6.1 Other TI Components Used in This Design
  12. 7Revision History

2.5 Reset

The Power-On-Reset net from the AM261x controlSOM, driven by the on-SOM push button or the AM261x SoC PORz signal is routed through SOM HD connector J1 and is tied to the reset logic for the following peripherals:

  • HSEC connector
  • OSPI Expansion connector reset
  • PHY1 reset
  • PHY2 reset
  • Ethernet add-on board connector reset

PORz is ANDed with each target peripheral's dedicated reset signal to drive the reset logic for each device.

  • MDIO0_MDIO - pinmuxed with the OSPI1_RESET_OUT0 signal from the AM261x SoC, routed through SOM HD connector J2 and passed through a resistor mux.
    • Note: The resistor to route OSPI1_RESET_OUT0 to the OSPI Expansion Connector is DNI by default, and must be populated for the reset signal to route to the OSPI Expansion Connector.
  • RGMII1_RST - AM261x controlSOM IO Expander output, input to reset logic for the RGMII1 PHY (PHY1)
  • MII_RST# - AM261x controlSOM IO Expander output, input to reset logic for the MII0 PHY (PHY1) and Ethernet add-on Board Connector

Figure 2-6 shows the reset architecture of the HSEC180ADAPEVM-AM2.

HSEC180ADAPEVM-AM2 HSEC180ADAPEVM-AM2 Reset Architecture Figure 2-6 HSEC180ADAPEVM-AM2 Reset Architecture