SPRUJF7 March   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
      2. 1.1.1 Sitara MCU+ Academy
      3. 1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Setup
    3. 2.3  Power Requirements
      1. 2.3.1 Power Tree
      2. 2.3.2 Power Sequence
    4. 2.4  Header Information
      1. 2.4.1 Baseboard Headers (J1, J2, J3)
      2. 2.4.2 HSEC Pinout
      3. 2.4.3 XDS Debug Header (J4)
      4. 2.4.4 FSI Header
      5. 2.4.5 OSPI Expansion Connector
      6. 2.4.6 Ethernet Add-on Board Connector
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  GPIO Mapping
    8. 2.8  Interfaces
      1. 2.8.1 USB
      2. 2.8.2 UART
      3. 2.8.3 FSI
      4. 2.8.4 OSPI
      5. 2.8.5 Ethernet
        1. 2.8.5.1 RGMII
        2. 2.8.5.2 PRU-ICSS
          1. 2.8.5.2.1 On-Board PHY
          2. 2.8.5.2.2 Ethernet Add-on Board
      6. 2.8.6 I2C
      7. 2.8.7 SPI
      8. 2.8.8 TMDSHSECDOCK-AM263 Peripherals
        1. 2.8.8.1 ADC/DAC
        2. 2.8.8.2 MCAN
        3. 2.8.8.3 LIN1
        4. 2.8.8.4 JTAG
        5. 2.8.8.5 GPIO
    9. 2.9  Debug Information
    10. 2.10 Test Points
    11. 2.11 Assembly Instructions
    12. 2.12 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References
    1. 6.1 Other TI Components Used in This Design
  12. 7Revision History

2.8.4 OSPI

The OSPI1 instance of the AM261x OSPI peripheral is routed to a 30-pin high density connector on the HSEC180ADAPEVM-AM2. Compatible OSPI add-on boards can be connected to the SOM to HSEC adapter board for interfacing with the AM261x MCU on the AM261x controlSOM.

Figure 2-12 shows the connections between the RGMII1 signals routed from the SOM HD connectors, the resistor muxing scheme, and connection to the OSPI expansion header. The OSPI1 reset logic is determined by the output of an AND gate with inputs PORz and OSPI1_RESET_OUT0.

HSEC180ADAPEVM-AM2 HSEC180ADAPEVM-AM2 OSPI Interface Figure 2-12 HSEC180ADAPEVM-AM2 OSPI Interface

The majority of the OSPI1 signals are pinmuxed with the RGMII signals on the AM261x MCU. The OSPI1_CSn1 signal is pinmuxed with EPWM7_A. In order to enable OSPI1 and route the OSPI1 nets to the OSPI Expansion connector, the following resistor modifications must be made:

Table 2-9 OSPI1 Resistor Mods
AM261x Signal Pinmuxed OSPI1 Signal DNI Resistor Populate Resistor
RGMII1_RXC OSPI1_CLK R25 R24
RGMII1_RX_CTL OSPI1_D0 R27 R26
RGMII1_RD0 OSPI1_D1 R29 R28
RGMII1_RD1 OSPI1_D2 R32 R30
RGMII1_RD2 OSPI1_D3 R34 R33
RGMII1_RD3 OSPI1_D4 R36 R35
RGMII1_TXC OSPI1_D5 R38 R37
RGMII1_TX_CTL OSPI1_D6 R46 R45
RGMII1_TD0 OSPI1_D7 R48 R47
RGMII1_TD1 OSPI1_CSn0 R50 R49
RGMII1_TD2 OSPI1_DQS R52 R51
RGMII1_TD3 OSPI1_ECC_FAIL R54 R53
MDIO0_MDIO OSPI1_RESET_OUT0 R56 R55
EPWM7_A OSPI1_CSn11 - R31
HSEC180ADAPEVM-AM2 OSPI1 - DNI Resistors Figure 2-13 OSPI1 - DNI Resistors
HSEC180ADAPEVM-AM2 OSPI1 - Install Resistors Figure 2-14 OSPI1 - Install Resistors