SPRUJF7 March   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
      2. 1.1.1 Sitara MCU+ Academy
      3. 1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Setup
    3. 2.3  Power Requirements
      1. 2.3.1 Power Tree
      2. 2.3.2 Power Sequence
    4. 2.4  Header Information
      1. 2.4.1 Baseboard Headers (J1, J2, J3)
      2. 2.4.2 HSEC Pinout
      3. 2.4.3 XDS Debug Header (J4)
      4. 2.4.4 FSI Header
      5. 2.4.5 OSPI Expansion Connector
      6. 2.4.6 Ethernet Add-on Board Connector
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  GPIO Mapping
    8. 2.8  Interfaces
      1. 2.8.1 USB
      2. 2.8.2 UART
      3. 2.8.3 FSI
      4. 2.8.4 OSPI
      5. 2.8.5 Ethernet
        1. 2.8.5.1 RGMII
        2. 2.8.5.2 PRU-ICSS
          1. 2.8.5.2.1 On-Board PHY
          2. 2.8.5.2.2 Ethernet Add-on Board
      6. 2.8.6 I2C
      7. 2.8.7 SPI
      8. 2.8.8 TMDSHSECDOCK-AM263 Peripherals
        1. 2.8.8.1 ADC/DAC
        2. 2.8.8.2 MCAN
        3. 2.8.8.3 LIN1
        4. 2.8.8.4 JTAG
        5. 2.8.8.5 GPIO
    9. 2.9  Debug Information
    10. 2.10 Test Points
    11. 2.11 Assembly Instructions
    12. 2.12 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References
    1. 6.1 Other TI Components Used in This Design
  12. 7Revision History

PRU-ICSS

The AM261x controlSOM routes two instances of the AM261x MCU on-die programmable real-time unit and industrial communication subsystem (PRU-ICSS) to the SOM HD connectors. On the HSEC180ADAPEVM-AM2, there are two external Ethernet ports - one on-board gigabit Ethernet PHY transceiver (DP83869), and one Ethernet add-on board connector. The gigabit Ethernet PHY is connected to the PR0_PRU0 core of the PRU-ICSS, and the Ethernet add-on board interface is connected to the PR0_PRU1 core of the PRU-ICSS. Table 2-12 details the protocols supported at each Ethernet port interface:

Table 2-12 PRU-ICSS Ethernet Protocols
AM261x PRU-ICSS Core On-board Peripheral / Speed External Interface Supported Protocols
PR0_PRU0
  • DP83869 gigabit PHY
  • 10/100/1000 Mbps
RJ45
  • PRU-ICSS RGMII/MII
  • CPSW RGMII/MII
PR0_PRU1
  • Ethernet add-on board connector
  • 10/100/1000 Mbps
Ethernet add-on board
  • PRU-ICSS RGMII/MII
HSEC180ADAPEVM-AM2 HSEC180ADAPEVM-AM2 PRU-ICSS Ethernet Implementation Figure 2-17 HSEC180ADAPEVM-AM2 PRU-ICSS Ethernet Implementation

The Ethernet data signals of the DP83869 PHY are terminated to a RJ45 connector. The RJ45 connector supports Ethernet speeds of 10/100/1000 Mbps connectivity and has integrated magnets and LEDs for link and activity indication.

There are a series of multiplexers on the paths of the PRU-ICSS nets from the SOM HD connectors to their external interfaces. 3 high-speed, 12-channel switches (TS3DDR3812) control the routing of the PRx_PRUx_GPIOx signals to either the Ethernet interfaces or to the HSEC connector. The select lines for the muxes are software controlled by two output signals configured by the on-SOM IO Expander, or hardware controlled by the on-board switches (SW3 and SW4) on the HSEC180ADAPEVM-AM2. An additional mux selects which set of MDIO signals is routed to the DP83869 PHY, and is dependent on which protocol is being used on the DP83869 - CPSW RGMII or PRU MII. The select line of this mux is controlled by AM261x GPIO74, which is routed from the MCU to the HSEC180ADAPEVM-AM2 through SOM HD connector J2. Table 2-13 shows the mux configurations. Figure 2-18 shows the mux select switches.

Table 2-13 PRU-ICSS Signal Routing
AM261x PRU-ICSS Core Destination Protocol MII0_MUX_SEL (SW3) MII1_MUX_SEL (SW4) MDIO/MDC MUX SEL
Controlled by controlSOM IO Expander OR on-board DIP Switches Controlled by AM261x GPIO74
PR0_PRU0 DP83869 PHY CPSW RGMII2 LOW / RIGHT (default) LOW / RIGHT (default) HIGH (AM261x SoC MDIO0 signals)
DP83869 PHY PRU MII0 LOW / RIGHT (default) LOW / RIGHT (default) LOW (default) (PRU MDIO0 signals)
HSEC CPSW RGMII HIGH / LEFT HIGH / LEFT HIGH (AM261x SoC MDIO0 signals)
HSEC PRU MII0 HIGH / LEFT HIGH / LEFT LOW (default) (PRU MDIO0 signals)
PR0_PRU1 Ethernet Add-on Board Connector PRU MII1 LOW / RIGHT (default) LOW / RIGHT (default) X
HSEC PRU MII1 HIGH / LEFT HIGH / LEFT X
HSEC180ADAPEVM-AM2 SW3/SW4 Positions Figure 2-18 SW3/SW4 Positions