SPRUJF7 March   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
      2. 1.1.1 Sitara MCU+ Academy
      3. 1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Setup
    3. 2.3  Power Requirements
      1. 2.3.1 Power Tree
      2. 2.3.2 Power Sequence
    4. 2.4  Header Information
      1. 2.4.1 Baseboard Headers (J1, J2, J3)
      2. 2.4.2 HSEC Pinout
      3. 2.4.3 XDS Debug Header (J4)
      4. 2.4.4 FSI Header
      5. 2.4.5 OSPI Expansion Connector
      6. 2.4.6 Ethernet Add-on Board Connector
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  GPIO Mapping
    8. 2.8  Interfaces
      1. 2.8.1 USB
      2. 2.8.2 UART
      3. 2.8.3 FSI
      4. 2.8.4 OSPI
      5. 2.8.5 Ethernet
        1. 2.8.5.1 RGMII
        2. 2.8.5.2 PRU-ICSS
          1. 2.8.5.2.1 On-Board PHY
          2. 2.8.5.2.2 Ethernet Add-on Board
      6. 2.8.6 I2C
      7. 2.8.7 SPI
      8. 2.8.8 TMDSHSECDOCK-AM263 Peripherals
        1. 2.8.8.1 ADC/DAC
        2. 2.8.8.2 MCAN
        3. 2.8.8.3 LIN1
        4. 2.8.8.4 JTAG
        5. 2.8.8.5 GPIO
    9. 2.9  Debug Information
    10. 2.10 Test Points
    11. 2.11 Assembly Instructions
    12. 2.12 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References
    1. 6.1 Other TI Components Used in This Design
  12. 7Revision History
2.8.5.2.1 On-Board PHY

The on-board DP83869 gigabit Ethernet PHY has the following hardware connections, shown in Figure 2-19 and detailed in Table 2-17.

HSEC180ADAPEVM-AM2 HSEC180ADAPEVM-AM2 On-Board PRU-ICSS PHY Figure 2-19 HSEC180ADAPEVM-AM2 On-Board PRU-ICSS PHY

Table 2-14 DP83869 Hardware Connections
DP83869 Pin AM261x / controlSOM Pin Source HSEC180ADAPEVM Net Notes
RX_D[0:3] PR0_PRU0_GPIO[0:3] ICSSM_MII0_RXD[0:3]
RX_CTRL/RX_DV PR0_PRU0_GPIO4 ICSSM_MII0_RX_DV
LED1/RX_ER PR0_PRU0_GPIO5 ICSSM_MII0_RXER
RX_CLK PR0_PRU0_GPIO6 ICSSM_MII0_RXCLK
LED_0 PR0_PRU0_GPIO8 ICSSM_MII0_RXLINK
TX_CTRL/TX_EN PR0_PRU0_GPIO15 ICSSM_MII0_TXEN
TX_CLK PR0_PRU0_GPIO16 ICSSM_MII0_TXCLK
TX_D[0:3] PR0_PRU0_GPIO[11:14] ICSSM_MII0_TXD[0:3]
MDC Output of MDIO/MDC Mux PR0_MDIO0_MDC_ON See Table 2-13
MDIO Output of MDIO/MDC Mux PR0_MDIO0_MDIO_ON See Table 2-13.
INT_N GPIO73 MII0_INTn
XI PHY0_25MHZ_CLK PHY0_25MHZ_CLK Output of Clock Buffer IC on AM261x controlSOM
RESET_N Output of MII_RST# AND PORz MII0/MII1_RST MII_RST# net sourced from IO Expander on AM261x controlSOM

The DP83869 PHY requires three separate power sources. VDDIO (3.3V) is the output of the on-board load switch, which uses the 3.3V system IO voltage as its input. The other two PHY power inputs - VDD1P1 and VDDA2P5 - are generated from on-board LDOs. For more on the system power, see Section 2.3.

Strapping Resistors

The DP83869 Ethernet PHY uses several functional pins as strap options to place the PHY into specific modes of operation. Each functional pin has a default mode that is driven by an internal pull resistor.

HSEC180ADAPEVM-AM2 DP83869 PHY Strapping Resistors Figure 2-20 DP83869 PHY Strapping Resistors

Table 2-15 PR0_PRU0 ICSS Gigabit Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode on HSEC180ADAPEVM-AM2 Function
RX_D0 0 3 PHY address: 0011
RX_D1 0 0
JTAG_TDO/GPIO_1 0 0 RGMII to Copper
RX_D3 0 0
RX_D2 0 0
LED_0 0 0 Auto-negotiation, 1000/100/10 advertised, auto MDI-X
RX_ER 0 0
LED_2 0 0
RX_DV 0 0 Port mirroring disabled
RJ45 Connector LED Indications

The RJ45 receptacle connected to the DP83869 PHY contains two bi-color LEDs that are used to indicate link and activity.

Table 2-16 PR0_PRU0 ICSS RJ45 Receptacle LED Indication
RJ45 LED Color Indication
Right LED GREEN Ethernet PHY power established
YELLOW Transmit or Receive activity
Left LED GREEN Link OK
YELLOW 1000BT link is up