TIDUF82B August   2024  – May 2025 DRV8162 , INA241A , ISOM8710

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Reference Design Overview
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Hardware Design
        1. 2.2.1.1 Power Stage Gate Driver
          1. 2.2.1.1.1 Gate Driver
          2. 2.2.1.1.2 Protection Features
          3. 2.2.1.1.3 VGVDD Definition
          4. 2.2.1.1.4 Strap Functions
        2. 2.2.1.2 Power Stage FETs
          1. 2.2.1.2.1 VGS versus RDS(ON)
        3. 2.2.1.3 Phase Current and Voltage Sensing
          1. 2.2.1.3.1 Phase A and Phase B Current Sensing
          2. 2.2.1.3.2 Phase C Current Sensing
          3. 2.2.1.3.3 Voltage Sensing
        4. 2.2.1.4 Host Processor Interface
        5. 2.2.1.5 Gate Drive Shutdown Path
        6. 2.2.1.6 System Diagnostic Measurements
          1. 2.2.1.6.1 Temperature Measurement
        7. 2.2.1.7 System Power Supply
          1. 2.2.1.7.1 12V Rail
          2. 2.2.1.7.2 3.3V Rail
      2. 2.2.2 Software Design
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8162L
      2. 2.3.2 INA241A
      3. 2.3.3 AMC0106M05
      4. 2.3.4 TPSM861253
      5. 2.3.5 LMR38010
      6. 2.3.6 TMP6131
      7. 2.3.7 ISOM8710
  9. 3Hardware, Software Test Requirements and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 PCB Overview
      2. 3.1.2 Hardware Configuration
        1. 3.1.2.1 Prerequisites
        2. 3.1.2.2 Default Resistor and Jumper Configuration
        3. 3.1.2.3 Connector
          1. 3.1.2.3.1 Host Processor Interface
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Power Management
        1. 3.3.1.1 Power Up
        2. 3.3.1.2 Power Down
      2. 3.3.2 Gate Voltage and Phase Voltage
        1. 3.3.2.1 20 VDC
        2. 3.3.2.2 48 VDC
        3. 3.3.2.3 60 VDC
      3. 3.3.3 Digital PWM and Gate Voltage
      4. 3.3.4 Phase-Current Measurements
      5. 3.3.5 System Test Results
        1. 3.3.5.1 Thermal Analysis
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors
  12. 6Revision History
3.1.2.3.1 Host Processor Interface

Table 3-3 shows the signals that the TIDA-010956 reference design uses to communicate with a C2000 LaunchPad of LAUNCHXL-F280039C.

Table 3-3 Pinout of J1 and J2 Host Processor Interface
LAUNCHXL-F280039CTIDA-010956
J5J7J8J6J1J2
3.3V5V(2)PWM7AGND3.3VNC(2)PWM_CHGND
ADCINC1(2)GNDPWM7BGPIO27(2)NC(2)GNDPWM_CLNC(2)
GPIO15ADCINB11PWM4AGPIO47LED4Vbus(1)PWM_BHFAULT
GPIO56(2)ADCINA10,
ADCINB1,
ADCINC10		PWM4BGPIO57(2)NC(2)V_C(1)PWM_BLNC(2)
GPIO56(2)ADCINA5PWM5AXRSn(2)NC(2)V_B(1)PWM_AHNC(2)
ADCINA9(2)ADCINA4,
ADCINB8		PWM5BSD2_D3NC(2)V_A(1)PWM_ALDAT_PhC
GPIO58(2)ADCINB4,
ADCINC8(2)		GPIO21(2)SD2_C3NC(2)NC(2)NC(2)SD_CLK
GPIO4ADCINB5EPWM1BGPIO20VDSLVLCCI_B(1)SD_CLK(1)EN_DRV
GPIO18ADCINA12,
ADCINC5		EPWM2AGPIO26VDSLVLCBI_A(1)CLK_PhC(1)PWM_EN
GPIO19ADCINA0,
ADCINB15,
ADCINC15		GPIO40(2)GPIO25(2)VDSLVLCATemperature(1)NC(2)NC(2)
(1) The signals shown in italic font are not tested in this design yet.
(2) The gray color code shows the pins which are Not Connected or reserved in the TIDA-010956 design.

Connections to the J5, J7 and J6, J8 are tested using a LAUNCHXL-F280039C as shown in Table 3-3. The TIDA-010956 can also be able to work with the J1, J3 and J2, J4 connectors of a LAUNCHXL-F280039C, or a LAUNCHXL-F28P65X LaunchPad.