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Product details

Parameters

Product type Retimer Number of channels (#) 4 Input compatibility AC-coupling, CML Speed (Max) (Gbps) 12.5 Protocols 10G-SR/LR, 40G-SR4/LR4, Infiniband, CPRI, Interlaken, General purpose Operating temperature range (C) -40 to 85 open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Features

  • Each Channel Independently Locks to Data Rates from 9.8 to 12.5 Gbps and Submultiples
  • Fast Lock Operation Based on Protocol-Select Mode
  • Low Latency (~300ps)
  • Adaptive Equalization up to 34-dB Boost at 5 GHz
  • Adjustable Transmit VOD: 600 to 1300 mVp-p
  • Adjustable Transmit De-emphasis to –15 dB
  • Typical Power Dissipation (EQ+DFE+CDR+DE): 180 mW/Channel
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection/Indicator
  • On-Chip Eye Monitor (EOM), PRBS Generator
  • Single 2.5-V ± 5% Power Supply
  • SMBus/EEPROM Configuration Modes
  • Operating Temperature Range of –40 to 85°C
  • WQFN 48-Pin 7-mm x 7-mm Package
  • Easy Pin Compatible Upgrade Between Repeater and Retimers
    • DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
    • DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps
    • DS110RT410 (EQ+CDR+DE): 8.5–11.3 Gbps
    • DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3 Gbps
    • DS125RT410 (EQ+CDR+DE): 9.8–12.5 Gbps
    • DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5 Gbps
    • DS100BR410 (EQ+DE): Up to 10.3125 Gbps

All trademarks are the property of their respective owners.

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Description

The DS125DF410 is four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10-15.

Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25 MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.

The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet DS125DF410 Low Power Multi-Rate Quad Channel Retimer datasheet (Rev. H) Feb. 27, 2018
Application notes Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications May 15, 2020
Application notes Implementing TI Retimers on 10G ZR and DWDM SFP+ Optical Links Apr. 08, 2019
Application notes DS110DF111,DS125DF111, DS100DF410, DS110DF410, and DS125DF410 Programming Guide Mar. 25, 2019
User guides DS100DF410EVK, DS110DF410EVK, DS125DF410EVM User's Guide (Rev. C) Jun. 22, 2016
Application notes Understanding EEPROM Programming for 10G to 12.5G Retimers Jan. 13, 2016
Application notes Selecting TI SigCon Devices for SFF-8431 SFP+ Applications May 06, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
699
Description

The DS125DF410EVM evaluation board lets you examine the advanced signal conditioning capabilities of the DS125DF410 and DS125RT410 devices using SMAs. The board is controlled by a PC using a USB port and the SigCon Architect GUI.

To use the SigCon Architect GUI to control the device, use the  (...)

Features
  • Each channel independently locks to 9.8 to 12.5 Gbps and sub-multiples of the data rates
  • Lock time operation (typically under 15 ms)
  • Low latency (300 ps)
  • Adjustable transmit VOD: 600 to 1300 mVp-p
  • Adjustable transmit de-emphasis to -12 dB
  • Typical power dissipation (EQ+DFE+CDR+DE): 180 mW per channel
  • (...)

Design tools & simulation

SIMULATION MODELS Download
SNLM143.PDF (25 KB) - IBIS Model
SIMULATION MODELS Download
SNLM150.PDF (25 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (RHS) 48 View options

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