Startseite Schnittstelle LVDS-, M-LVDS- und PECL-ICs

DS92LV1260

AKTIV

6-kanaliger Deserializer, 10 Bit, für Channel-Link-B-LVDS

Produktdetails

Function Deserializer Protocols Channel-Link I Number of transmitters 10 Number of receivers 6 Supply voltage (V) 3.3 Signaling rate (MBits) 2400 Input signal BLVDS, LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Deserializer Protocols Channel-Link I Number of transmitters 10 Number of receivers 6 Supply voltage (V) 3.3 Signaling rate (MBits) 2400 Input signal BLVDS, LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NZH) 196 225 mm² 15 x 15
  • Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks
  • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams
  • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input
  • Parallel Clock Rate up to 40MHz
  • On Chip Filtering for PLL
  • Absolute Maximum Worst Case Power Dissipation = 1.9W at 3.6V
  • High Impedance Inputs Upon Power Off (Vcc = 0V)
  • Single Power Supply at +3.3V
  • 196-pin NFBGA Package (Low-profile Ball Grid Array) Package
  • Industrial Temperature Range Operation: −40°C to +85°C

All trademarks are the property of their respective owners.

  • Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks
  • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams
  • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input
  • Parallel Clock Rate up to 40MHz
  • On Chip Filtering for PLL
  • Absolute Maximum Worst Case Power Dissipation = 1.9W at 3.6V
  • High Impedance Inputs Upon Power Off (Vcc = 0V)
  • Single Power Supply at +3.3V
  • 196-pin NFBGA Package (Low-profile Ball Grid Array) Package
  • Industrial Temperature Range Operation: −40°C to +85°C

All trademarks are the property of their respective owners.

The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the Texas Instruments DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also includes a seventh serial input channel that serves as a redundant input.

Each deserializer block in the DS92LV1260 operates independently with its own clock recovery circuitry and lock-detect signaling.

The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.

The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the Texas Instruments DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also includes a seventh serial input channel that serves as a redundant input.

Each deserializer block in the DS92LV1260 operates independently with its own clock recovery circuitry and lock-detect signaling.

The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 2
Typ Titel Datum
* Data sheet DS92LV1260 Six Channel 10 Bit BLVDS Deserializer datasheet (Rev. F) 16 Apr 2013
Application note How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) 26 Apr 2013

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese voll ausgestattete Design- und Simulationssuite verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
Simulationstool

TINA-TI — SPICE-basiertes analoges Simulationsprogramm

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Benutzerhandbuch: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
NFBGA (NZH) 196 Ultra Librarian

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos