The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.
The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.
| Top-Dokumentation | Typ | Titel | Format-Optionen | Datum |
|---|---|---|---|---|
| * | Data sheet | LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs datasheet (Rev. J) | 19 Sep 2011 | |
| User guide | LMK040xx Evaluation Board User's Guide (Rev. B) | 08 Jan 2015 | ||
| Application note | AN-1734 Using the LMK03000C to Clean Recovered Clocks (Rev. B) | 26 Apr 2013 | ||
| Application note | AN-1821 CPRI Repeater System (Rev. A) | 26 Apr 2013 | ||
| Application note | AN-1865 Frequency Synthesis and Planning for PLL Architectures (Rev. C) | 26 Apr 2013 | ||
| Application note | AN-1910 LMK04000 Family Phase Noise Characterization (Rev. A) | 26 Apr 2013 | ||
| Application note | AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) | 26 Apr 2013 | ||
| Application note | Phase Synchronization with Multiple Devices and Frequencies (Rev. A) | 26 Apr 2013 | ||
| Design guide | Clock Conditioner Owner's Manual | 10 Nov 2006 |
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The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
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