*FAST is a Registered Trademark of Fairchild Semicondutor Corp.
The RCA-CD54/74AC373 and CD54/74AC533 and the CD54/74ACT373 and CD54/74ACT533 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\) is HIGH. When the Latch Enable (LE\) goes LOW, the data is latched. The Output Enable (OE\) controls the 3-sate outputs. When the Output Enable (OE\) is HIGH, the outputs are in the high-impedance state. The latch operation is independent of the state of the Output Enable.
The CD74AC/ACT373 and CD74AC/ACT533 are supplied in 20-lead dual-in-line plastic package (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commerical (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).
The CD54AC/ACT373 and CD54AC/ACT533, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | Octal Transparent Latch, 3-State datasheet | 03 dic 1998 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 dic 2022 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 jun 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 jun 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 abr 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| PDIP (N) | 20 | Ver opciones |
| SOIC (DW) | 20 | Ver opciones |
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