The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data
transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts
48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential
Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent
during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps,
providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also
supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate
of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output
LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link
devices.
The LDI chipset is improved over prior generations of FPD-Link devices and offers higher
bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth,
the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides
additional output current during transitions to counteract cable loading effects. DC balancing on a
cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis
and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/−1
LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in
length to be driven. This chipset is an ideal means to solve EMI and cable size problems for
high-resolution flat panel applications. It provides a reliable interface based on LVDS technology
that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and
keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to
.
The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data
transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts
48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential
Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent
during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps,
providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also
supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate
of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output
LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link
devices.
The LDI chipset is improved over prior generations of FPD-Link devices and offers higher
bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth,
the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides
additional output current during transitions to counteract cable loading effects. DC balancing on a
cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis
and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/−1
LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in
length to be driven. This chipset is an ideal means to solve EMI and cable size problems for
high-resolution flat panel applications. It provides a reliable interface based on LVDS technology
that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and
keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to
.